[PATCH] D62519: AMDGPU: Don't enable all lanes with non-CSR VGPR spills
Stanislav Mekhanoshin via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed May 29 11:19:02 PDT 2019
rampitec added a comment.
JBTW, strictly speaking you do not need a full wave and 256 bytes of scratch loads and stores per VGPR. Only first min(wavefrontsize, # of SGPRs spilled) lanes are needed.
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