[PATCH] D62592: [RISCV] Add assembler support for RVC HINT instructions
Luís Marques via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed May 29 07:17:08 PDT 2019
luismarques created this revision.
luismarques added reviewers: asb, rogfer01, shiva0217.
Herald added subscribers: llvm-commits, benna, psnobl, jocewei, PkmX, rkruppe, the_o, brucehoult, MartinMosbeck, edward-jones, zzheng, jrtc27, kito-cheng, niosHD, sabuasal, apazos, simoncook, johnrusso, rbar.
Herald added a project: LLVM.
Adds assembler support for RVC HINT instructions. Adding MC support will probably require adding (target-independent?) support for disambiguating instructions based on the non-overlapping operand classes used in the regular vs hint instructions, since otherwise the instructions are bit-identical.
The hint instructions are enabled by default (if the standard C extension is enabled). To disable them pass `-mattr=-rvc-hints`. This "enabled by default" behavior was achieved by adding the `FeatureRVCHints` to the RV32/RV64 `ProcessorModel`s. Setting the `RISCVSubtarget` member flags default value to true doesn't work for all tool flows (e.g. using `llvm-mc` for a .s -> .o).
The (non-hint) C_NOP definition now has a `let Inst{6-2} = 0`. That's necessary to ensure that e.g. `c.addi x0, 7` would not be decoded as a plain `c.nop`. With the added let statement it's now (correctly) decoded as `unknown`. When MC support for the hint instructions is eventually added it should decode as `c.nop 7`.
The (non-hint) `C_ADDI_NOP` instruction is also added by this patch, since it fits the overall theme of the patch. That instruction definition is necessary to add support for writing a `c.nop` in its extended form of `c.addi x0, 0`.
Repository:
rL LLVM
https://reviews.llvm.org/D62592
Files:
lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
lib/Target/RISCV/RISCV.td
lib/Target/RISCV/RISCVInstrInfo.td
lib/Target/RISCV/RISCVInstrInfoC.td
lib/Target/RISCV/RISCVRegisterInfo.td
lib/Target/RISCV/RISCVSubtarget.h
test/MC/RISCV/rv32c-invalid.s
test/MC/RISCV/rv64c-hints-valid.s
test/MC/RISCV/rvc-hints-invalid.s
test/MC/RISCV/rvc-hints-valid.s
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