[llvm] r361933 - [AArch64][SVE2] Asm: support SVE2 Floating Point Pairwise Group
Cullen Rhodes via llvm-commits
llvm-commits at lists.llvm.org
Wed May 29 01:40:33 PDT 2019
Author: c-rhodes
Date: Wed May 29 01:40:33 2019
New Revision: 361933
URL: http://llvm.org/viewvc/llvm-project?rev=361933&view=rev
Log:
[AArch64][SVE2] Asm: support SVE2 Floating Point Pairwise Group
Summary:
Patch adds support for the following instructions:
SVE2 floating-point pairwise operations:
* FADDP, FMAXNMP, FMINNMP, FMAXP, FMINP
The specification can be found here:
https://developer.arm.com/docs/ddi0602/latest
Reviewed By: chill
Differential Revision: https://reviews.llvm.org/D62383
Added:
llvm/trunk/test/MC/AArch64/SVE2/faddp-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE2/faddp.s
llvm/trunk/test/MC/AArch64/SVE2/fmaxnmp-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE2/fmaxnmp.s
llvm/trunk/test/MC/AArch64/SVE2/fmaxp-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE2/fmaxp.s
llvm/trunk/test/MC/AArch64/SVE2/fminnmp-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE2/fminnmp.s
llvm/trunk/test/MC/AArch64/SVE2/fminp-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE2/fminp.s
Modified:
llvm/trunk/lib/Target/AArch64/AArch64SVEInstrInfo.td
llvm/trunk/lib/Target/AArch64/SVEInstrFormats.td
Modified: llvm/trunk/lib/Target/AArch64/AArch64SVEInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64SVEInstrInfo.td?rev=361933&r1=361932&r2=361933&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64SVEInstrInfo.td (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64SVEInstrInfo.td Wed May 29 01:40:33 2019
@@ -1294,6 +1294,13 @@ let Predicates = [HasSVE2] in {
defm FCVTNT_ZPmZ : sve2_fp_convert_down_narrow<"fcvtnt">;
defm FCVTLT_ZPmZ : sve2_fp_convert_up_long<"fcvtlt">;
+ // SVE2 floating-point pairwise operations
+ defm FADDP_ZPmZZ : sve2_fp_pairwise_pred<0b000, "faddp">;
+ defm FMAXNMP_ZPmZZ : sve2_fp_pairwise_pred<0b100, "fmaxnmp">;
+ defm FMINNMP_ZPmZZ : sve2_fp_pairwise_pred<0b101, "fminnmp">;
+ defm FMAXP_ZPmZZ : sve2_fp_pairwise_pred<0b110, "fmaxp">;
+ defm FMINP_ZPmZZ : sve2_fp_pairwise_pred<0b111, "fminp">;
+
// Predicated shifts
defm SQSHL_ZPmI : sve_int_bin_pred_shift_imm_left< 0b0110, "sqshl">;
defm UQSHL_ZPmI : sve_int_bin_pred_shift_imm_left< 0b0111, "uqshl">;
Modified: llvm/trunk/lib/Target/AArch64/SVEInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/SVEInstrFormats.td?rev=361933&r1=361932&r2=361933&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/SVEInstrFormats.td (original)
+++ llvm/trunk/lib/Target/AArch64/SVEInstrFormats.td Wed May 29 01:40:33 2019
@@ -1473,6 +1473,39 @@ multiclass sve2_fp_convert_down_odd_roun
}
//===----------------------------------------------------------------------===//
+// SVE2 Floating Point Pairwise Group
+//===----------------------------------------------------------------------===//
+
+class sve2_fp_pairwise_pred<bits<2> sz, bits<3> opc, string asm,
+ ZPRRegOp zprty>
+: I<(outs zprty:$Zdn), (ins PPR3bAny:$Pg, zprty:$_Zdn, zprty:$Zm),
+ asm, "\t$Zdn, $Pg/m, $_Zdn, $Zm",
+ "",
+ []>, Sched<[]> {
+ bits<3> Pg;
+ bits<5> Zm;
+ bits<5> Zdn;
+ let Inst{31-24} = 0b01100100;
+ let Inst{23-22} = sz;
+ let Inst{21-19} = 0b010;
+ let Inst{18-16} = opc;
+ let Inst{15-13} = 0b100;
+ let Inst{12-10} = Pg;
+ let Inst{9-5} = Zm;
+ let Inst{4-0} = Zdn;
+
+ let Constraints = "$Zdn = $_Zdn";
+ let DestructiveInstType = Destructive;
+ let ElementSize = zprty.ElementSize;
+}
+
+multiclass sve2_fp_pairwise_pred<bits<3> opc, string asm> {
+ def _H : sve2_fp_pairwise_pred<0b01, opc, asm, ZPR16>;
+ def _S : sve2_fp_pairwise_pred<0b10, opc, asm, ZPR32>;
+ def _D : sve2_fp_pairwise_pred<0b11, opc, asm, ZPR64>;
+}
+
+//===----------------------------------------------------------------------===//
// SVE Stack Allocation Group
//===----------------------------------------------------------------------===//
Added: llvm/trunk/test/MC/AArch64/SVE2/faddp-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE2/faddp-diagnostics.s?rev=361933&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE2/faddp-diagnostics.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE2/faddp-diagnostics.s Wed May 29 01:40:33 2019
@@ -0,0 +1,50 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Source and Destination Registers must match
+
+faddp z0.h, p0/m, z1.h, z2.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
+// CHECK-NEXT: faddp z0.h, p0/m, z1.h, z2.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Invalid element width
+
+faddp z0.b, p0/m, z0.b, z1.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: faddp z0.b, p0/m, z0.b, z1.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Element sizes must match
+
+faddp z0.h, p0/m, z0.s, z1.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: faddp z0.h, p0/m, z0.s, z1.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+faddp z0.h, p0/m, z0.h, z1.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: faddp z0.h, p0/m, z0.h, z1.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Invalid predicate operation
+
+faddp z0.h, p0/z, z0.h, z1.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: faddp z0.h, p0/z, z0.h, z1.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Predicate not in restricted predicate range
+
+faddp z0.h, p8/m, z0.h, z1.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: faddp z0.h, p8/m, z0.h, z1.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
Added: llvm/trunk/test/MC/AArch64/SVE2/faddp.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE2/faddp.s?rev=361933&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE2/faddp.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE2/faddp.s Wed May 29 01:40:33 2019
@@ -0,0 +1,53 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
+// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
+// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+faddp z0.h, p0/m, z0.h, z1.h
+// CHECK-INST: faddp z0.h, p0/m, z0.h, z1.h
+// CHECK-ENCODING: [0x20,0x80,0x50,0x64]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 20 80 50 64 <unknown>
+
+faddp z29.s, p3/m, z29.s, z30.s
+// CHECK-INST: faddp z29.s, p3/m, z29.s, z30.s
+// CHECK-ENCODING: [0xdd,0x8f,0x90,0x64]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: dd 8f 90 64 <unknown>
+
+faddp z31.d, p7/m, z31.d, z30.d
+// CHECK-INST: faddp z31.d, p7/m, z31.d, z30.d
+// CHECK-ENCODING: [0xdf,0x9f,0xd0,0x64]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: df 9f d0 64 <unknown>
+
+// --------------------------------------------------------------------------//
+// Test compatibility with MOVPRFX instruction.
+
+movprfx z31.d, p0/z, z6.d
+// CHECK-INST: movprfx z31.d, p0/z, z6.d
+// CHECK-ENCODING: [0xdf,0x20,0xd0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: df 20 d0 04 <unknown>
+
+faddp z31.d, p0/m, z31.d, z30.d
+// CHECK-INST: faddp z31.d, p0/m, z31.d, z30.d
+// CHECK-ENCODING: [0xdf,0x83,0xd0,0x64]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: df 83 d0 64 <unknown>
+
+movprfx z31, z6
+// CHECK-INST: movprfx z31, z6
+// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: df bc 20 04 <unknown>
+
+faddp z31.d, p7/m, z31.d, z30.d
+// CHECK-INST: faddp z31.d, p7/m, z31.d, z30.d
+// CHECK-ENCODING: [0xdf,0x9f,0xd0,0x64]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: df 9f d0 64 <unknown>
Added: llvm/trunk/test/MC/AArch64/SVE2/fmaxnmp-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE2/fmaxnmp-diagnostics.s?rev=361933&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE2/fmaxnmp-diagnostics.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE2/fmaxnmp-diagnostics.s Wed May 29 01:40:33 2019
@@ -0,0 +1,50 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Source and Destination Registers must match
+
+fmaxnmp z0.h, p0/m, z1.h, z2.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
+// CHECK-NEXT: fmaxnmp z0.h, p0/m, z1.h, z2.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Invalid element width
+
+fmaxnmp z0.b, p0/m, z0.b, z1.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: fmaxnmp z0.b, p0/m, z0.b, z1.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Element sizes must match
+
+fmaxnmp z0.h, p0/m, z0.s, z1.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: fmaxnmp z0.h, p0/m, z0.s, z1.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fmaxnmp z0.h, p0/m, z0.h, z1.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: fmaxnmp z0.h, p0/m, z0.h, z1.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Invalid predicate operation
+
+fmaxnmp z0.h, p0/z, z0.h, z1.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: fmaxnmp z0.h, p0/z, z0.h, z1.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Predicate not in restricted predicate range
+
+fmaxnmp z0.h, p8/m, z0.h, z1.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: fmaxnmp z0.h, p8/m, z0.h, z1.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
Added: llvm/trunk/test/MC/AArch64/SVE2/fmaxnmp.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE2/fmaxnmp.s?rev=361933&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE2/fmaxnmp.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE2/fmaxnmp.s Wed May 29 01:40:33 2019
@@ -0,0 +1,53 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
+// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
+// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+fmaxnmp z0.h, p0/m, z0.h, z1.h
+// CHECK-INST: fmaxnmp z0.h, p0/m, z0.h, z1.h
+// CHECK-ENCODING: [0x20,0x80,0x54,0x64]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 20 80 54 64 <unknown>
+
+fmaxnmp z29.s, p3/m, z29.s, z30.s
+// CHECK-INST: fmaxnmp z29.s, p3/m, z29.s, z30.s
+// CHECK-ENCODING: [0xdd,0x8f,0x94,0x64]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: dd 8f 94 64 <unknown>
+
+fmaxnmp z31.d, p7/m, z31.d, z30.d
+// CHECK-INST: fmaxnmp z31.d, p7/m, z31.d, z30.d
+// CHECK-ENCODING: [0xdf,0x9f,0xd4,0x64]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: df 9f d4 64 <unknown>
+
+// --------------------------------------------------------------------------//
+// Test compatibility with MOVPRFX instruction.
+
+movprfx z31.d, p0/z, z6.d
+// CHECK-INST: movprfx z31.d, p0/z, z6.d
+// CHECK-ENCODING: [0xdf,0x20,0xd0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: df 20 d0 04 <unknown>
+
+fmaxnmp z31.d, p0/m, z31.d, z30.d
+// CHECK-INST: fmaxnmp z31.d, p0/m, z31.d, z30.d
+// CHECK-ENCODING: [0xdf,0x83,0xd4,0x64]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: df 83 d4 64 <unknown>
+
+movprfx z31, z6
+// CHECK-INST: movprfx z31, z6
+// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: df bc 20 04 <unknown>
+
+fmaxnmp z31.d, p7/m, z31.d, z30.d
+// CHECK-INST: fmaxnmp z31.d, p7/m, z31.d, z30.d
+// CHECK-ENCODING: [0xdf,0x9f,0xd4,0x64]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: df 9f d4 64 <unknown>
Added: llvm/trunk/test/MC/AArch64/SVE2/fmaxp-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE2/fmaxp-diagnostics.s?rev=361933&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE2/fmaxp-diagnostics.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE2/fmaxp-diagnostics.s Wed May 29 01:40:33 2019
@@ -0,0 +1,50 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Source and Destination Registers must match
+
+fmaxp z0.h, p0/m, z1.h, z2.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
+// CHECK-NEXT: fmaxp z0.h, p0/m, z1.h, z2.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Invalid element width
+
+fmaxp z0.b, p0/m, z0.b, z1.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: fmaxp z0.b, p0/m, z0.b, z1.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Element sizes must match
+
+fmaxp z0.h, p0/m, z0.s, z1.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: fmaxp z0.h, p0/m, z0.s, z1.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fmaxp z0.h, p0/m, z0.h, z1.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: fmaxp z0.h, p0/m, z0.h, z1.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Invalid predicate operation
+
+fmaxp z0.h, p0/z, z0.h, z1.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: fmaxp z0.h, p0/z, z0.h, z1.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Predicate not in restricted predicate range
+
+fmaxp z0.h, p8/m, z0.h, z1.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: fmaxp z0.h, p8/m, z0.h, z1.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
Added: llvm/trunk/test/MC/AArch64/SVE2/fmaxp.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE2/fmaxp.s?rev=361933&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE2/fmaxp.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE2/fmaxp.s Wed May 29 01:40:33 2019
@@ -0,0 +1,53 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
+// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
+// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+fmaxp z0.h, p0/m, z0.h, z1.h
+// CHECK-INST: fmaxp z0.h, p0/m, z0.h, z1.h
+// CHECK-ENCODING: [0x20,0x80,0x56,0x64]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 20 80 56 64 <unknown>
+
+fmaxp z29.s, p3/m, z29.s, z30.s
+// CHECK-INST: fmaxp z29.s, p3/m, z29.s, z30.s
+// CHECK-ENCODING: [0xdd,0x8f,0x96,0x64]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: dd 8f 96 64 <unknown>
+
+fmaxp z31.d, p7/m, z31.d, z30.d
+// CHECK-INST: fmaxp z31.d, p7/m, z31.d, z30.d
+// CHECK-ENCODING: [0xdf,0x9f,0xd6,0x64]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: df 9f d6 64 <unknown>
+
+// --------------------------------------------------------------------------//
+// Test compatibility with MOVPRFX instruction.
+
+movprfx z31.d, p0/z, z6.d
+// CHECK-INST: movprfx z31.d, p0/z, z6.d
+// CHECK-ENCODING: [0xdf,0x20,0xd0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: df 20 d0 04 <unknown>
+
+fmaxp z31.d, p0/m, z31.d, z30.d
+// CHECK-INST: fmaxp z31.d, p0/m, z31.d, z30.d
+// CHECK-ENCODING: [0xdf,0x83,0xd6,0x64]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: df 83 d6 64 <unknown>
+
+movprfx z31, z6
+// CHECK-INST: movprfx z31, z6
+// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: df bc 20 04 <unknown>
+
+fmaxp z31.d, p7/m, z31.d, z30.d
+// CHECK-INST: fmaxp z31.d, p7/m, z31.d, z30.d
+// CHECK-ENCODING: [0xdf,0x9f,0xd6,0x64]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: df 9f d6 64 <unknown>
Added: llvm/trunk/test/MC/AArch64/SVE2/fminnmp-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE2/fminnmp-diagnostics.s?rev=361933&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE2/fminnmp-diagnostics.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE2/fminnmp-diagnostics.s Wed May 29 01:40:33 2019
@@ -0,0 +1,50 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Source and Destination Registers must match
+
+fminnmp z0.h, p0/m, z1.h, z2.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
+// CHECK-NEXT: fminnmp z0.h, p0/m, z1.h, z2.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Invalid element width
+
+fminnmp z0.b, p0/m, z0.b, z1.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: fminnmp z0.b, p0/m, z0.b, z1.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Element sizes must match
+
+fminnmp z0.h, p0/m, z0.s, z1.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: fminnmp z0.h, p0/m, z0.s, z1.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fminnmp z0.h, p0/m, z0.h, z1.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: fminnmp z0.h, p0/m, z0.h, z1.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Invalid predicate operation
+
+fminnmp z0.h, p0/z, z0.h, z1.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: fminnmp z0.h, p0/z, z0.h, z1.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Predicate not in restricted predicate range
+
+fminnmp z0.h, p8/m, z0.h, z1.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: fminnmp z0.h, p8/m, z0.h, z1.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
Added: llvm/trunk/test/MC/AArch64/SVE2/fminnmp.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE2/fminnmp.s?rev=361933&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE2/fminnmp.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE2/fminnmp.s Wed May 29 01:40:33 2019
@@ -0,0 +1,53 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
+// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
+// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+fminnmp z0.h, p0/m, z0.h, z1.h
+// CHECK-INST: fminnmp z0.h, p0/m, z0.h, z1.h
+// CHECK-ENCODING: [0x20,0x80,0x55,0x64]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 20 80 55 64 <unknown>
+
+fminnmp z29.s, p3/m, z29.s, z30.s
+// CHECK-INST: fminnmp z29.s, p3/m, z29.s, z30.s
+// CHECK-ENCODING: [0xdd,0x8f,0x95,0x64]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: dd 8f 95 64 <unknown>
+
+fminnmp z31.d, p7/m, z31.d, z30.d
+// CHECK-INST: fminnmp z31.d, p7/m, z31.d, z30.d
+// CHECK-ENCODING: [0xdf,0x9f,0xd5,0x64]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: df 9f d5 64 <unknown>
+
+// --------------------------------------------------------------------------//
+// Test compatibility with MOVPRFX instruction.
+
+movprfx z31.d, p0/z, z6.d
+// CHECK-INST: movprfx z31.d, p0/z, z6.d
+// CHECK-ENCODING: [0xdf,0x20,0xd0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: df 20 d0 04 <unknown>
+
+fminnmp z31.d, p0/m, z31.d, z30.d
+// CHECK-INST: fminnmp z31.d, p0/m, z31.d, z30.d
+// CHECK-ENCODING: [0xdf,0x83,0xd5,0x64]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: df 83 d5 64 <unknown>
+
+movprfx z31, z6
+// CHECK-INST: movprfx z31, z6
+// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: df bc 20 04 <unknown>
+
+fminnmp z31.d, p7/m, z31.d, z30.d
+// CHECK-INST: fminnmp z31.d, p7/m, z31.d, z30.d
+// CHECK-ENCODING: [0xdf,0x9f,0xd5,0x64]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: df 9f d5 64 <unknown>
Added: llvm/trunk/test/MC/AArch64/SVE2/fminp-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE2/fminp-diagnostics.s?rev=361933&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE2/fminp-diagnostics.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE2/fminp-diagnostics.s Wed May 29 01:40:33 2019
@@ -0,0 +1,50 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Source and Destination Registers must match
+
+fminp z0.h, p0/m, z1.h, z2.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
+// CHECK-NEXT: fminp z0.h, p0/m, z1.h, z2.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Invalid element width
+
+fminp z0.b, p0/m, z0.b, z1.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: fminp z0.b, p0/m, z0.b, z1.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Element sizes must match
+
+fminp z0.h, p0/m, z0.s, z1.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: fminp z0.h, p0/m, z0.s, z1.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fminp z0.h, p0/m, z0.h, z1.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: fminp z0.h, p0/m, z0.h, z1.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Invalid predicate operation
+
+fminp z0.h, p0/z, z0.h, z1.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: fminp z0.h, p0/z, z0.h, z1.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Predicate not in restricted predicate range
+
+fminp z0.h, p8/m, z0.h, z1.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: fminp z0.h, p8/m, z0.h, z1.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
Added: llvm/trunk/test/MC/AArch64/SVE2/fminp.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE2/fminp.s?rev=361933&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE2/fminp.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE2/fminp.s Wed May 29 01:40:33 2019
@@ -0,0 +1,53 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
+// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
+// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+fminp z0.h, p0/m, z0.h, z1.h
+// CHECK-INST: fminp z0.h, p0/m, z0.h, z1.h
+// CHECK-ENCODING: [0x20,0x80,0x57,0x64]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 20 80 57 64 <unknown>
+
+fminp z29.s, p3/m, z29.s, z30.s
+// CHECK-INST: fminp z29.s, p3/m, z29.s, z30.s
+// CHECK-ENCODING: [0xdd,0x8f,0x97,0x64]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: dd 8f 97 64 <unknown>
+
+fminp z31.d, p7/m, z31.d, z30.d
+// CHECK-INST: fminp z31.d, p7/m, z31.d, z30.d
+// CHECK-ENCODING: [0xdf,0x9f,0xd7,0x64]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: df 9f d7 64 <unknown>
+
+// --------------------------------------------------------------------------//
+// Test compatibility with MOVPRFX instruction.
+
+movprfx z31.d, p0/z, z6.d
+// CHECK-INST: movprfx z31.d, p0/z, z6.d
+// CHECK-ENCODING: [0xdf,0x20,0xd0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: df 20 d0 04 <unknown>
+
+fminp z31.d, p0/m, z31.d, z30.d
+// CHECK-INST: fminp z31.d, p0/m, z31.d, z30.d
+// CHECK-ENCODING: [0xdf,0x83,0xd7,0x64]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: df 83 d7 64 <unknown>
+
+movprfx z31, z6
+// CHECK-INST: movprfx z31, z6
+// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: df bc 20 04 <unknown>
+
+fminp z31.d, p7/m, z31.d, z30.d
+// CHECK-INST: fminp z31.d, p7/m, z31.d, z30.d
+// CHECK-ENCODING: [0xdf,0x9f,0xd7,0x64]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: df 9f d7 64 <unknown>
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