[llvm] r361918 - Revert "[X86] Use 'llvm_unreachable' instead of nullptr in unreachable code to"

[Craig Topper via llvm-commits]

Revert commit messages should use svn revision numbers not git commit hash.

They should also include a reason for revert.

On Tue, May 28, 2019 at 7:46 PM Pengfei Wang via llvm-commits <
llvm-commits at lists.llvm.org> wrote:

> Author: pengfei
> Date: Tue May 28 19:49:59 2019
> New Revision: 361918
>
> URL: http://llvm.org/viewvc/llvm-project?rev=361918&view=rev
> Log:
> Revert "[X86] Use 'llvm_unreachable' instead of nullptr in unreachable
> code to"
>
> This reverts commit c1b3716614bc0a107e6f41a7d3d503baefad8a5b.
>
> Modified:
>     llvm/trunk/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp
>     llvm/trunk/lib/Target/X86/X86InstructionSelector.cpp
>
> Modified: llvm/trunk/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp?rev=361918&r1=361917&r2=361918&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp (original)
> +++ llvm/trunk/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp Tue May 28
> 19:49:59 2019
> @@ -91,9 +91,7 @@ RegisterBankInfo::getRegBank(unsigned Re
>      return RB;
>    if (auto *RC = RegClassOrBank.dyn_cast<const TargetRegisterClass *>())
>      return &getRegBankFromRegClass(*RC);
> -
> -  llvm_unreachable("RegClassOrBank is either a const RegisterBank* or "
> -                   "a const TargetRegisterClass*");
> +  return nullptr;
>  }
>
>  const TargetRegisterClass &
>
> Modified: llvm/trunk/lib/Target/X86/X86InstructionSelector.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstructionSelector.cpp?rev=361918&r1=361917&r2=361918&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86InstructionSelector.cpp (original)
> +++ llvm/trunk/lib/Target/X86/X86InstructionSelector.cpp Tue May 28
> 19:49:59 2019
> @@ -1610,8 +1610,8 @@ bool X86InstructionSelector::selectDivRe
>    assert(RegTy == MRI.getType(Op1Reg) && RegTy == MRI.getType(Op2Reg) &&
>           "Arguments and return value types must match");
>
> -  const RegisterBank &RegRB = *RBI.getRegBank(DstReg, MRI, TRI);
> -  if (RegRB.getID() != X86::GPRRegBankID)
> +  const RegisterBank *RegRB = RBI.getRegBank(DstReg, MRI, TRI);
> +  if (!RegRB || RegRB->getID() != X86::GPRRegBankID)
>      return false;
>
>    const static unsigned NumTypes = 4; // i8, i16, i32, i64
> @@ -1709,7 +1709,7 @@ bool X86InstructionSelector::selectDivRe
>    const DivRemEntry &TypeEntry = *OpEntryIt;
>    const DivRemEntry::DivRemResult &OpEntry =
> TypeEntry.ResultTable[OpIndex];
>
> -  const TargetRegisterClass *RegRC = getRegClass(RegTy, RegRB);
> +  const TargetRegisterClass *RegRC = getRegClass(RegTy, *RegRB);
>    if (!RBI.constrainGenericRegister(Op1Reg, *RegRC, MRI) ||
>        !RBI.constrainGenericRegister(Op2Reg, *RegRC, MRI) ||
>        !RBI.constrainGenericRegister(DstReg, *RegRC, MRI)) {
>
>
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-- 
~Craig
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