[PATCH] D62519: AMDGPU: Don't enable all lanes with non-CSR VGPR spills

[Stanislav Mekhanoshin via Phabricator via llvm-commits]

rampitec added a comment.

In D62519#1519387 <https://reviews.llvm.org/D62519#1519387>, @arsenm wrote:

> In D62519#1519365 <https://reviews.llvm.org/D62519#1519365>, @rampitec wrote:
>
> > In D62519#1519360 <https://reviews.llvm.org/D62519#1519360>, @arsenm wrote:
> >
> > > In D62519#1519357 <https://reviews.llvm.org/D62519#1519357>, @rampitec wrote:
> > >
> > > > LGTM, but I still believe it shall be reserved register instead.
> > >
> > >
> > > I'm not sure what you mean. A reserved register wouldn't help
> >
> >
> > It would help if we can reserve it in both caller and callee, right?
>
>
> Not sure what register you mean. Reserving registers generally causes more problems that it solves. Reserving VGPRs for SGPR spills would require reserving 2 to cover all possible SGPR spills


I mean we can do it conditionally if we have a call stack. Normally you would only need one VGPR, but again that requires whole program analysis.


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