[PATCH] D62519: AMDGPU: Don't enable all lanes with non-CSR VGPR spills

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added a comment.

In D62519#1519357 <https://reviews.llvm.org/D62519#1519357>, @rampitec wrote:

> LGTM, but I still believe it shall be reserved register instead.


I'm not sure what you mean. A reserved register wouldn't help


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