[PATCH] D62415: [X86-64] Fix 256-bit SET0 lowering for non-VLX targets

[David Greene via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL361843: [X86-64] Fix 256-bit SET0 lowering for non-VLX targets (authored by greened, committed by ).

Changed prior to commit:
  https://reviews.llvm.org/D62415?vs=201468&id=201683#toc

Repository:
  rL LLVM

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D62415/new/

https://reviews.llvm.org/D62415

Files:
  llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
  llvm/trunk/test/CodeGen/X86/avx512f-256-set0.mir


Index: llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
===================================================================
--- llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
@@ -3932,6 +3932,12 @@
       MIB.addReg(SrcReg, RegState::ImplicitDefine);
       return true;
     }
+    if (MI.getOpcode() == X86::AVX512_256_SET0) {
+      // No VLX so we must reference a zmm.
+      unsigned ZReg =
+        TRI->getMatchingSuperReg(SrcReg, X86::sub_ymm, &X86::VR512RegClass);
+      MIB->getOperand(0).setReg(ZReg);
+    }
     return Expand2AddrUndef(MIB, get(X86::VPXORDZrr));
   }
   case X86::V_SETALLONES:
Index: llvm/trunk/test/CodeGen/X86/avx512f-256-set0.mir
===================================================================
--- llvm/trunk/test/CodeGen/X86/avx512f-256-set0.mir
+++ llvm/trunk/test/CodeGen/X86/avx512f-256-set0.mir
@@ -0,0 +1,66 @@
+# Test that we emit VPXORD with ZMM registers instead of YMM
+# registers when we do not have VLX.
+#
+# RUN: llc -mtriple=x86_64-- -mattr=+avx512f -o - %s | FileCheck %s
+# CHECK: vpxord %zmm16, %zmm16, %zmm16
+--- |
+  ; ModuleID = 'test.ll'
+  source_filename = "test.ll"
+  target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
+  target triple = "x86_64-unknown-linux-gnu"
+
+  @tst_ = common global [4 x i64] zeroinitializer, align 64
+
+  define void @main() #0 {
+  bb0:
+    %gep1 = bitcast [4 x i64]* @tst_ to [4 x i64]*
+    %lsr.iv1 = bitcast [4 x i64]* %gep1 to <4 x i64>*
+    store <4 x i64> zeroinitializer, <4 x i64>* %lsr.iv1, align 16
+    ret void
+  }
+
+  attributes #0 = { "target-features"="+avx512f" }
+
+...
+---
+name:            main
+alignment:       4
+exposesReturnsTwice: false
+legalized:       false
+regBankSelected: false
+selected:        false
+failedISel:      false
+tracksRegLiveness: true
+hasWinCFI:       false
+registers:       []
+liveins:         []
+frameInfo:
+  isFrameAddressTaken: false
+  isReturnAddressTaken: false
+  hasStackMap:     false
+  hasPatchPoint:   false
+  stackSize:       0
+  offsetAdjustment: 0
+  maxAlignment:    0
+  adjustsStack:    false
+  hasCalls:        false
+  stackProtector:  ''
+  maxCallFrameSize: 0
+  cvBytesOfCalleeSavedRegisters: 0
+  hasOpaqueSPAdjustment: false
+  hasVAStart:      false
+  hasMustTailInVarArgFunc: false
+  localFrameSize:  0
+  savePoint:       ''
+  restorePoint:    ''
+fixedStack:      []
+stack:           []
+constants:       []
+machineFunctionInfo: {}
+body:             |
+  bb.0.bb0:
+    renamable $ymm16 = AVX512_256_SET0
+    VMOVAPSZmr $rip, 1, $noreg, @tst_, $noreg, killed renamable $zmm16 :: (store 32 into %ir.lsr.iv1, align 64)
+    RET 0
+
+...


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