[PATCH] D62366: [X86] VP2INTERSECT llvm

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: test/CodeGen/X86/inline-asm-avx512f-x-constraint.ll:6
+; The old check is
+; INLINEASM &"vpaddq\09$3, $2, $0 {$1}", 0, 7340042, def %{{.*}}, 1179657, %{{.*}}, 7340041, %[[REG1]], 7340041, %[[REG2]], 12, implicit-def early-clobber $df, 12, implicit-def early-clobber $fpsw, 12, implicit-def early-clobber $eflags
+; but when we adjust X86RegisterInfo.td for example add/rewirte RegisterClass, it may change the RegisterClass value due to order. In fact here really we need to check is like this:
----------------
I don't think these comments are necessary. Just update update the CHECK.


Repository:
  rL LLVM

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D62366/new/

https://reviews.llvm.org/D62366