[llvm] r361770 - [AMDGPU] Fix for the address sanitizer failure caused by the ifollowing commit:

[Alexander Timofeev via llvm-commits]

Author: alex-t
Date: Mon May 27 08:03:29 2019
New Revision: 361770

URL: http://llvm.org/viewvc/llvm-project?rev=361770&view=rev
Log:
    [AMDGPU] Fix for the address sanitizer failure caused by the ifollowing commit:

    1a8b2ea611cf4ca7cb09562e0238cfefa27c05b5  Divergence driven ISel. Assign register class for cross block values according to the divergence.

Modified:
    llvm/trunk/lib/Target/AMDGPU/SIFixSGPRCopies.cpp

Modified: llvm/trunk/lib/Target/AMDGPU/SIFixSGPRCopies.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIFixSGPRCopies.cpp?rev=361770&r1=361769&r2=361770&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIFixSGPRCopies.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/SIFixSGPRCopies.cpp Mon May 27 08:03:29 2019
@@ -595,7 +595,9 @@ bool SIFixSGPRCopies::runOnMachineFuncti
 
             unsigned OpNo = UseMI->getOperandNo(&Use);
             const MCInstrDesc &Desc = TII->get(UseMI->getOpcode());
-            if (Desc.OpInfo && Desc.OpInfo[OpNo].RegClass != -1) {
+            if (!Desc.isPseudo() && Desc.OpInfo &&
+                OpNo <= Desc.getNumOperands() &&
+                Desc.OpInfo[OpNo].RegClass != -1) {
               const TargetRegisterClass *OpRC =
                   TRI->getRegClass(Desc.OpInfo[OpNo].RegClass);
               if (!TRI->isSGPRClass(OpRC) && OpRC != &AMDGPU::VS_32RegClass &&