[llvm] r361740 - [MCA][Scheduler] Improved critical memory dependency computation.

[Andrea Di Biagio via llvm-commits]

Author: adibiagio
Date: Sun May 26 12:50:31 2019
New Revision: 361740

URL: http://llvm.org/viewvc/llvm-project?rev=361740&view=rev
Log:
[MCA][Scheduler] Improved critical memory dependency computation.

This fixes a problem where back-pressure increases caused by register
dependencies were not correctly notified if execution was also delayed by memory
dependencies.

Modified:
    llvm/trunk/lib/MCA/HardwareUnits/Scheduler.cpp
    llvm/trunk/test/tools/llvm-mca/X86/BtVer2/bottleneck-hints-3.s

Modified: llvm/trunk/lib/MCA/HardwareUnits/Scheduler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MCA/HardwareUnits/Scheduler.cpp?rev=361740&r1=361739&r2=361740&view=diff
==============================================================================
--- llvm/trunk/lib/MCA/HardwareUnits/Scheduler.cpp (original)
+++ llvm/trunk/lib/MCA/HardwareUnits/Scheduler.cpp Sun May 26 12:50:31 2019
@@ -105,7 +105,13 @@ void Scheduler::issueInstruction(
   // other dependent instructions. Dependent instructions may be issued during
   // this same cycle if operands have ReadAdvance entries.  Promote those
   // instructions to the ReadySet and notify the caller that those are ready.
-  if (HasDependentUsers && promoteToPendingSet(PendingInstructions))
+  // If IR is a memory operation, then always call method `promoteToReadySet()`
+  // to notify any dependent memory operations that IR started execution.
+  bool ShouldPromoteInstructions = Inst.isMemOp();
+  if (HasDependentUsers)
+    ShouldPromoteInstructions |= promoteToPendingSet(PendingInstructions);
+
+  if (ShouldPromoteInstructions)
     promoteToReadySet(ReadyInstructions);
 }
 
@@ -287,15 +293,19 @@ uint64_t Scheduler::analyzeResourcePress
 void Scheduler::analyzeDataDependencies(SmallVectorImpl<InstRef> &RegDeps,
                                         SmallVectorImpl<InstRef> &MemDeps) {
   const auto EndIt = PendingSet.end() - NumDispatchedToThePendingSet;
-  for (InstRef &IR : make_range(PendingSet.begin(), EndIt)) {
-    Instruction &IS = *IR.getInstruction();
+  for (const InstRef &IR : make_range(PendingSet.begin(), EndIt)) {
+    const Instruction &IS = *IR.getInstruction();
     if (Resources->checkAvailability(IS.getDesc()))
       continue;
 
-    if (IS.isReady() || (IS.isMemOp() && LSU.isReady(IR) != IR))
-      MemDeps.emplace_back(IR);
-    else
+    const CriticalDependency &CMD = IS.getCriticalMemDep();
+    if (IS.isMemOp() && IS.getCurrentMemDep() != &IS && !CMD.Cycles)
+      continue;
+
+    if (IS.isPending())
       RegDeps.emplace_back(IR);
+    if (CMD.Cycles)
+      MemDeps.emplace_back(IR);
   }
 }
 

Modified: llvm/trunk/test/tools/llvm-mca/X86/BtVer2/bottleneck-hints-3.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/tools/llvm-mca/X86/BtVer2/bottleneck-hints-3.s?rev=361740&r1=361739&r2=361740&view=diff
==============================================================================
--- llvm/trunk/test/tools/llvm-mca/X86/BtVer2/bottleneck-hints-3.s (original)
+++ llvm/trunk/test/tools/llvm-mca/X86/BtVer2/bottleneck-hints-3.s Sun May 26 12:50:31 2019
@@ -24,7 +24,7 @@ vmovaps %xmm0, 48(%rdi)
 # CHECK-NEXT: Throughput Bottlenecks:
 # CHECK-NEXT:   Resource Pressure       [ 0.00% ]
 # CHECK-NEXT:   Data Dependencies:      [ 99.89% ]
-# CHECK-NEXT:   - Register Dependencies [ 0.00% ]
+# CHECK-NEXT:   - Register Dependencies [ 83.24% ]
 # CHECK-NEXT:   - Memory Dependencies   [ 99.89% ]
 
 # CHECK:      Instruction Info: