[llvm] r361718 - [ARM] Select a number of fp16 rounding functions
David Green via llvm-commits
llvm-commits at lists.llvm.org
Sun May 26 04:13:00 PDT 2019
Author: dmgreen
Date: Sun May 26 04:13:00 2019
New Revision: 361718
URL: http://llvm.org/viewvc/llvm-project?rev=361718&view=rev
Log:
[ARM] Select a number of fp16 rounding functions
This add patterns for fp16 round and ceil etc. Same as the float and double
patterns.
Differential Revision: https://reviews.llvm.org/D62326
Modified:
llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
llvm/trunk/lib/Target/ARM/ARMInstrVFP.td
llvm/trunk/test/CodeGen/ARM/fp16-fullfp16.ll
llvm/trunk/test/CodeGen/ARM/fp16-instructions.ll
Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=361718&r1=361717&r2=361718&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Sun May 26 04:13:00 2019
@@ -1156,6 +1156,8 @@ ARMTargetLowering::ARMTargetLowering(con
setOperationAction(ISD::FLOG, MVT::f16, Promote);
setOperationAction(ISD::FLOG10, MVT::f16, Promote);
setOperationAction(ISD::FLOG2, MVT::f16, Promote);
+
+ setOperationAction(ISD::FROUND, MVT::f16, Legal);
}
if (Subtarget->hasNEON()) {
Modified: llvm/trunk/lib/Target/ARM/ARMInstrVFP.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrVFP.td?rev=361718&r1=361717&r2=361718&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrVFP.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrVFP.td Sun May 26 04:13:00 2019
@@ -930,9 +930,9 @@ def VNEGH : AHuI<0b11101, 0b11, 0b0001,
multiclass vrint_inst_zrx<string opc, bit op, bit op2, SDPatternOperator node> {
def H : AHuI<0b11101, 0b11, 0b0110, 0b11, 0,
- (outs SPR:$Sd), (ins SPR:$Sm),
+ (outs HPR:$Sd), (ins HPR:$Sm),
NoItinerary, !strconcat("vrint", opc), ".f16\t$Sd, $Sm",
- []>,
+ [(set (f16 HPR:$Sd), (node (f16 HPR:$Sm)))]>,
Requires<[HasFullFP16]> {
let Inst{7} = op2;
let Inst{16} = op;
@@ -975,9 +975,9 @@ multiclass vrint_inst_anpm<string opc, b
let PostEncoderMethod = "", DecoderNamespace = "VFPV8",
isUnpredicable = 1 in {
def H : AHuInp<0b11101, 0b11, 0b1000, 0b01, 0,
- (outs SPR:$Sd), (ins SPR:$Sm),
+ (outs HPR:$Sd), (ins HPR:$Sm),
NoItinerary, !strconcat("vrint", opc, ".f16\t$Sd, $Sm"),
- []>,
+ [(set (f16 HPR:$Sd), (node (f16 HPR:$Sm)))]>,
Requires<[HasFullFP16]> {
let Inst{17-16} = rm;
}
Modified: llvm/trunk/test/CodeGen/ARM/fp16-fullfp16.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fp16-fullfp16.ll?rev=361718&r1=361717&r2=361718&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/fp16-fullfp16.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/fp16-fullfp16.ll Sun May 26 04:13:00 2019
@@ -488,53 +488,77 @@ define void @test_copysign(half* %p, hal
ret void
}
-; FIXME
-;define void @test_floor(half* %p) {
-; %a = load half, half* %p, align 2
-; %r = call half @llvm.floor.f16(half %a)
-; store half %r, half* %p
-; ret void
-;}
-
-; FIXME
-;define void @test_ceil(half* %p) {
-; %a = load half, half* %p, align 2
-; %r = call half @llvm.ceil.f16(half %a)
-; store half %r, half* %p
-; ret void
-;}
-
-; FIXME
-;define void @test_trunc(half* %p) {
-; %a = load half, half* %p, align 2
-; %r = call half @llvm.trunc.f16(half %a)
-; store half %r, half* %p
-; ret void
-;}
-
-; FIXME
-;define void @test_rint(half* %p) {
-; %a = load half, half* %p, align 2
-; %r = call half @llvm.rint.f16(half %a)
-; store half %r, half* %p
-; ret void
-;}
-
-; FIXME
-;define void @test_nearbyint(half* %p) {
-; %a = load half, half* %p, align 2
-; %r = call half @llvm.nearbyint.f16(half %a)
-; store half %r, half* %p
-; ret void
-;}
-
-; FIXME
-;define void @test_round(half* %p) {
-; %a = load half, half* %p, align 2
-; %r = call half @llvm.round.f16(half %a)
-; store half %r, half* %p
-; ret void
-;}
+define void @test_floor(half* %p) {
+; CHECK-LABEL: test_floor:
+; CHECK: vldr.16 s0, [r0]
+; CHECK-NEXT: vrintm.f16 s0, s0
+; CHECK-NEXT: vstr.16 s0, [r0]
+; CHECK-NEXT: bx lr
+ %a = load half, half* %p, align 2
+ %r = call half @llvm.floor.f16(half %a)
+ store half %r, half* %p
+ ret void
+}
+
+define void @test_ceil(half* %p) {
+; CHECK-LABEL: test_ceil:
+; CHECK: vldr.16 s0, [r0]
+; CHECK-NEXT: vrintp.f16 s0, s0
+; CHECK-NEXT: vstr.16 s0, [r0]
+; CHECK-NEXT: bx lr
+ %a = load half, half* %p, align 2
+ %r = call half @llvm.ceil.f16(half %a)
+ store half %r, half* %p
+ ret void
+}
+
+define void @test_trunc(half* %p) {
+; CHECK-LABEL: test_trunc:
+; CHECK: vldr.16 s0, [r0]
+; CHECK-NEXT: vrintz.f16 s0, s0
+; CHECK-NEXT: vstr.16 s0, [r0]
+; CHECK-NEXT: bx lr
+ %a = load half, half* %p, align 2
+ %r = call half @llvm.trunc.f16(half %a)
+ store half %r, half* %p
+ ret void
+}
+
+define void @test_rint(half* %p) {
+; CHECK-LABEL: test_rint:
+; CHECK: vldr.16 s0, [r0]
+; CHECK-NEXT: vrintx.f16 s0, s0
+; CHECK-NEXT: vstr.16 s0, [r0]
+; CHECK-NEXT: bx lr
+ %a = load half, half* %p, align 2
+ %r = call half @llvm.rint.f16(half %a)
+ store half %r, half* %p
+ ret void
+}
+
+define void @test_nearbyint(half* %p) {
+; CHECK-LABEL: test_nearbyint:
+; CHECK: vldr.16 s0, [r0]
+; CHECK-NEXT: vrintr.f16 s0, s0
+; CHECK-NEXT: vstr.16 s0, [r0]
+; CHECK-NEXT: bx lr
+ %a = load half, half* %p, align 2
+ %r = call half @llvm.nearbyint.f16(half %a)
+ store half %r, half* %p
+ ret void
+}
+
+define void @test_round(half* %p) {
+; CHECK-LABEL: test_round:
+; CHECK: vldr.16 s0, [r0]
+; CHECK-NEXT: vrinta.f16 s0, s0
+; CHECK-NEXT: vstr.16 s0, [r0]
+; CHECK-NEXT: bx lr
+ %a = load half, half* %p, align 2
+ %r = call half @llvm.round.f16(half %a)
+ store half %r, half* %p
+ ret void
+}
define void @test_fmuladd(half* %p, half* %q, half* %r) {
; CHECK-LABEL: test_fmuladd:
Modified: llvm/trunk/test/CodeGen/ARM/fp16-instructions.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fp16-instructions.ll?rev=361718&r1=361717&r2=361718&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/fp16-instructions.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/fp16-instructions.ll Sun May 26 04:13:00 2019
@@ -43,8 +43,6 @@ entry:
; CHECK-HARDFP-FULLFP16: {{.*}} lr
}
-; 1. VABS: TODO
-
; 2. VADD
define float @Add(float %a.coerce, float %b.coerce) {
entry:
@@ -691,15 +689,6 @@ entry:
; CHECK-HARDFP-FULLFP16: vnmul.f16 s0, s0, s1
}
-; TODO:
-; 28. VRINTA
-; 29. VRINTM
-; 30. VRINTN
-; 31. VRINTP
-; 32. VRINTR
-; 33. VRINTX
-; 34. VRINTZ
-
; 35. VSELEQ
define half @select_cc1(half* %a0) {
%1 = load half, half* %a0
@@ -955,8 +944,6 @@ entry:
; CHECK-SOFTFP-FP16-T32-NEXT: vcvtb.f16.f32 s0, [[S4]]
}
-; 39. VSQRT - TODO
-
; 40. VSUB
define float @Sub(float %a.coerce, float %b.coerce) {
entry:
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