[llvm] r361697 - [NFC] Make tests more robust for new optimizations
David Bolvansky via llvm-commits
llvm-commits at lists.llvm.org
Sat May 25 07:10:20 PDT 2019
Author: xbolva00
Date: Sat May 25 07:10:20 2019
New Revision: 361697
URL: http://llvm.org/viewvc/llvm-project?rev=361697&view=rev
Log:
[NFC] Make tests more robust for new optimizations
Modified:
llvm/trunk/test/CodeGen/ARM/crash-greedy.ll
llvm/trunk/test/CodeGen/Hexagon/bit-visit-flowq.ll
llvm/trunk/test/CodeGen/Hexagon/rdf-ignore-undef.ll
llvm/trunk/test/CodeGen/Hexagon/reg-scavengebug.ll
llvm/trunk/test/CodeGen/Hexagon/regalloc-block-overlap.ll
llvm/trunk/test/Transforms/LoopVectorize/if-pred-stores.ll
Modified: llvm/trunk/test/CodeGen/ARM/crash-greedy.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/crash-greedy.ll?rev=361697&r1=361696&r2=361697&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/crash-greedy.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/crash-greedy.ll Sat May 25 07:10:20 2019
@@ -7,11 +7,11 @@ target triple = "thumbv7-apple-darwin"
declare double @exp(double)
; CHECK: remat_subreg
-define void @remat_subreg(float* nocapture %x, i32* %y, i32 %n, i32 %z, float %c, float %lambda, float* nocapture %ret_f, float* nocapture %ret_df) nounwind {
+define void @remat_subreg(float* nocapture %x, i32* %y, i32 %n, i32 %z, float %c, float %lambda, float* nocapture %ret_f, float* nocapture %ret_df, i1 %cond) nounwind {
entry:
%conv16 = fpext float %lambda to double
%mul17 = fmul double %conv16, -1.000000e+00
- br i1 undef, label %cond.end.us, label %cond.end
+ br i1 %cond, label %cond.end.us, label %cond.end
cond.end.us: ; preds = %entry
unreachable
Modified: llvm/trunk/test/CodeGen/Hexagon/bit-visit-flowq.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/bit-visit-flowq.ll?rev=361697&r1=361696&r2=361697&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/bit-visit-flowq.ll (original)
+++ llvm/trunk/test/CodeGen/Hexagon/bit-visit-flowq.ll Sat May 25 07:10:20 2019
@@ -9,7 +9,7 @@ target triple = "hexagon"
@debug = external hidden unnamed_addr global i1, align 4
; Function Attrs: nounwind
-define void @foo() local_unnamed_addr #0 {
+define void @foo(i1 %cond) local_unnamed_addr #0 {
entry:
br label %if.end5
@@ -17,14 +17,14 @@ if.end5:
br i1 undef, label %if.then12, label %if.end13
if.then12: ; preds = %if.end5
- unreachable
+ ret void
if.end13: ; preds = %if.end5
br label %for.cond
for.cond: ; preds = %if.end13
%or.cond288 = or i1 undef, undef
- br i1 undef, label %if.then44, label %if.end51
+ br i1 %cond, label %if.then44, label %if.end51
if.then44: ; preds = %for.cond
tail call void @bar() #0
Modified: llvm/trunk/test/CodeGen/Hexagon/rdf-ignore-undef.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/rdf-ignore-undef.ll?rev=361697&r1=361696&r2=361697&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/rdf-ignore-undef.ll (original)
+++ llvm/trunk/test/CodeGen/Hexagon/rdf-ignore-undef.ll Sat May 25 07:10:20 2019
@@ -49,7 +49,7 @@ if.end88.do.body_crit_edge:
br label %do.body
if.then124: ; preds = %if.end88, %do.body
- unreachable
+ ret i32 0
}
attributes #0 = { nounwind }
Modified: llvm/trunk/test/CodeGen/Hexagon/reg-scavengebug.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/reg-scavengebug.ll?rev=361697&r1=361696&r2=361697&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/reg-scavengebug.ll (original)
+++ llvm/trunk/test/CodeGen/Hexagon/reg-scavengebug.ll Sat May 25 07:10:20 2019
@@ -19,7 +19,7 @@ declare <16 x i32> @llvm.hexagon.V6.vali
declare <16 x i32> @llvm.hexagon.V6.vaddh(<16 x i32>, <16 x i32>) #0
; Function Attrs: nounwind
-define void @f0(i16* noalias nocapture %a0, i32* noalias nocapture readonly %a1, i32 %a2, i8* noalias nocapture readonly %a3) #1 {
+define void @f0(i16* noalias nocapture %a0, i32* noalias nocapture readonly %a1, i32 %a2, i8* noalias nocapture readonly %a3, i1 %cond) #1 {
b0:
%v0 = add nsw i32 %a2, 63
%v1 = ashr i32 %v0, 6
@@ -40,7 +40,7 @@ b1:
%v13 = getelementptr inbounds i32, i32* %a1, i32 48
%v14 = tail call <16 x i32> @llvm.hexagon.V6.vaddh(<16 x i32> %v12, <16 x i32> undef)
%v15 = bitcast i32* %v13 to <16 x i32>*
- br i1 undef, label %b2, label %b3
+ br i1 %cond, label %b2, label %b3
b2: ; preds = %b1
%v16 = getelementptr inbounds <16 x i32>, <16 x i32>* %v15, i32 1
Modified: llvm/trunk/test/CodeGen/Hexagon/regalloc-block-overlap.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/regalloc-block-overlap.ll?rev=361697&r1=361696&r2=361697&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/regalloc-block-overlap.ll (original)
+++ llvm/trunk/test/CodeGen/Hexagon/regalloc-block-overlap.ll Sat May 25 07:10:20 2019
@@ -16,7 +16,7 @@ declare <32 x i32> @llvm.hexagon.V6.vasr
declare <64 x i32> @llvm.hexagon.V6.vlutvwh.128B(<32 x i32>, <32 x i32>, i32) #1
declare <64 x i32> @llvm.hexagon.V6.vlutvwh.oracc.128B(<64 x i32>, <32 x i32>, <32 x i32>, i32) #1
-define hidden void @fred(<32 x i32>* %a0, i32 %a1) #0 {
+define hidden void @fred(<32 x i32>* %a0, i32 %a1, i1 %cond) #0 {
b0:
%v1 = ashr i32 %a1, 7
%v2 = shl nsw i32 %v1, 7
@@ -70,7 +70,7 @@ b15:
br label %b16
b16: ; preds = %b15
- br i1 undef, label %b17, label %b18
+ br i1 %cond, label %b17, label %b18
b17: ; preds = %b16
unreachable
Modified: llvm/trunk/test/Transforms/LoopVectorize/if-pred-stores.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/LoopVectorize/if-pred-stores.ll?rev=361697&r1=361696&r2=361697&view=diff
==============================================================================
--- llvm/trunk/test/Transforms/LoopVectorize/if-pred-stores.ll (original)
+++ llvm/trunk/test/Transforms/LoopVectorize/if-pred-stores.ll Sat May 25 07:10:20 2019
@@ -194,9 +194,11 @@ for.end:
; vectorized loop body.
; PR18724
-define void @bug18724() {
+define void @bug18724(i1 %cond) {
; UNROLL-LABEL: @bug18724(
; UNROLL-NEXT: entry:
+; UNROLL-NEXT: [[TMP0:%.*]] = xor i1 [[COND:%.*]], true
+; UNROLL-NEXT: call void @llvm.assume(i1 [[TMP0]])
; UNROLL-NEXT: br label [[FOR_BODY14:%.*]]
; UNROLL: for.body14:
; UNROLL-NEXT: [[INDVARS_IV3:%.*]] = phi i64 [ [[INDVARS_IV_NEXT4:%.*]], [[FOR_INC23:%.*]] ], [ undef, [[ENTRY:%.*]] ]
@@ -211,13 +213,16 @@ define void @bug18724() {
; UNROLL: for.inc23:
; UNROLL-NEXT: [[INEWCHUNKS_2]] = phi i32 [ [[INC21]], [[IF_THEN18]] ], [ [[INEWCHUNKS_120]], [[FOR_BODY14]] ]
; UNROLL-NEXT: [[INDVARS_IV_NEXT4]] = add nsw i64 [[INDVARS_IV3]], 1
+; UNROLL-NEXT: [[TMP1:%.*]] = trunc i64 [[INDVARS_IV3]] to i32
+; UNROLL-NEXT: [[CMP13:%.*]] = icmp slt i32 [[TMP1]], 0
+; UNROLL-NEXT: call void @llvm.assume(i1 [[CMP13]])
; UNROLL-NEXT: br label [[FOR_BODY14]]
;
; UNROLL-NOSIMPLIFY-LABEL: @bug18724(
; UNROLL-NOSIMPLIFY-NEXT: entry:
; UNROLL-NOSIMPLIFY-NEXT: br label [[FOR_BODY9:%.*]]
; UNROLL-NOSIMPLIFY: for.body9:
-; UNROLL-NOSIMPLIFY-NEXT: br i1 undef, label [[FOR_INC26:%.*]], label [[FOR_BODY14_PREHEADER:%.*]]
+; UNROLL-NOSIMPLIFY-NEXT: br i1 [[COND:%.*]], label [[FOR_INC26:%.*]], label [[FOR_BODY14_PREHEADER:%.*]]
; UNROLL-NOSIMPLIFY: for.body14.preheader:
; UNROLL-NOSIMPLIFY-NEXT: br i1 true, label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]]
; UNROLL-NOSIMPLIFY: vector.ph:
@@ -287,6 +292,8 @@ define void @bug18724() {
;
; VEC-LABEL: @bug18724(
; VEC-NEXT: entry:
+; VEC-NEXT: [[TMP0:%.*]] = xor i1 [[COND:%.*]], true
+; VEC-NEXT: call void @llvm.assume(i1 [[TMP0]])
; VEC-NEXT: br label [[FOR_BODY14:%.*]]
; VEC: for.body14:
; VEC-NEXT: [[INDVARS_IV3:%.*]] = phi i64 [ [[INDVARS_IV_NEXT4:%.*]], [[FOR_INC23:%.*]] ], [ undef, [[ENTRY:%.*]] ]
@@ -301,13 +308,16 @@ define void @bug18724() {
; VEC: for.inc23:
; VEC-NEXT: [[INEWCHUNKS_2]] = phi i32 [ [[INC21]], [[IF_THEN18]] ], [ [[INEWCHUNKS_120]], [[FOR_BODY14]] ]
; VEC-NEXT: [[INDVARS_IV_NEXT4]] = add nsw i64 [[INDVARS_IV3]], 1
+; VEC-NEXT: [[TMP1:%.*]] = trunc i64 [[INDVARS_IV3]] to i32
+; VEC-NEXT: [[CMP13:%.*]] = icmp slt i32 [[TMP1]], 0
+; VEC-NEXT: call void @llvm.assume(i1 [[CMP13]])
; VEC-NEXT: br label [[FOR_BODY14]]
;
entry:
br label %for.body9
for.body9:
- br i1 undef, label %for.inc26, label %for.body14
+ br i1 %cond, label %for.inc26, label %for.body14
for.body14:
%indvars.iv3 = phi i64 [ %indvars.iv.next4, %for.inc23 ], [ undef, %for.body9 ]
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