[PATCH] D62415: [X86-64] Fix 256-bit SET0 lowering for non-VLX targets

[David Greene via Phabricator via llvm-commits]

greened created this revision.
greened added reviewers: dtemirbulatov, craig.topper, RKSimon.
Herald added subscribers: llvm-commits, hiraditya.
Herald added a project: LLVM.

If we don't have VLX then 256-bit SET0 should be lowered to VPXOR with ZMM registers.  This restores functionality accidentally removed by r309926.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D62415

Files:
  llvm/lib/Target/X86/X86InstrInfo.cpp


Index: llvm/lib/Target/X86/X86InstrInfo.cpp
===================================================================
--- llvm/lib/Target/X86/X86InstrInfo.cpp
+++ llvm/lib/Target/X86/X86InstrInfo.cpp
@@ -3932,6 +3932,12 @@
       MIB.addReg(SrcReg, RegState::ImplicitDefine);
       return true;
     }
+    if (MI.getOpcode() == X86::AVX512_256_SET0) {
+      // No VLX so we must reference a zmm.
+      unsigned ZReg =
+        TRI->getMatchingSuperReg(SrcReg, X86::sub_ymm, &X86::VR512RegClass);
+      MIB->getOperand(0).setReg(ZReg);
+    }
     return Expand2AddrUndef(MIB, get(X86::VPXORDZrr));
   }
   case X86::V_SETALLONES:


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