[PATCH] D59990: AMDGPU. Divergence driven ISel. Assign register class for cross block values according to the divergence.

[Alexander via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL361644: [AMDGPU] Divergence driven ISel. Assign register class for cross block values… (authored by alex-t, committed by ).
Herald added a project: LLVM.

Changed prior to commit:
  https://reviews.llvm.org/D59990?vs=200995&id=201259#toc

Repository:
  rL LLVM

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D59990/new/

https://reviews.llvm.org/D59990

Files:
  llvm/trunk/include/llvm/CodeGen/FunctionLoweringInfo.h
  llvm/trunk/include/llvm/CodeGen/SelectionDAG.h
  llvm/trunk/include/llvm/CodeGen/TargetLowering.h
  llvm/trunk/include/llvm/CodeGen/TargetRegisterInfo.h
  llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  llvm/trunk/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp
  llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
  llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.h
  llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
  llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
  llvm/trunk/lib/Target/AMDGPU/SIFixSGPRCopies.cpp
  llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp
  llvm/trunk/lib/Target/AMDGPU/SIISelLowering.h
  llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp
  llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.h
  llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
  llvm/trunk/lib/Target/ARM/ARMISelLowering.h
  llvm/trunk/test/CodeGen/AMDGPU/atomicrmw-nand.ll
  llvm/trunk/test/CodeGen/AMDGPU/branch-relaxation.ll
  llvm/trunk/test/CodeGen/AMDGPU/branch-uniformity.ll
  llvm/trunk/test/CodeGen/AMDGPU/control-flow-fastregalloc.ll
  llvm/trunk/test/CodeGen/AMDGPU/divergent-branch-uniform-condition.ll
  llvm/trunk/test/CodeGen/AMDGPU/extract_subvector_vec4_vec3.ll
  llvm/trunk/test/CodeGen/AMDGPU/fabs.ll
  llvm/trunk/test/CodeGen/AMDGPU/fdiv32-to-rcp-folding.ll
  llvm/trunk/test/CodeGen/AMDGPU/fmin_legacy.ll
  llvm/trunk/test/CodeGen/AMDGPU/fneg-fabs.ll
  llvm/trunk/test/CodeGen/AMDGPU/fsub.ll
  llvm/trunk/test/CodeGen/AMDGPU/i1-copy-from-loop.ll
  llvm/trunk/test/CodeGen/AMDGPU/i1-copy-phi-uniform-branch.ll
  llvm/trunk/test/CodeGen/AMDGPU/insert_vector_elt.ll
  llvm/trunk/test/CodeGen/AMDGPU/llvm.amdgcn.div.scale.ll
  llvm/trunk/test/CodeGen/AMDGPU/llvm.amdgcn.fmed3.ll
  llvm/trunk/test/CodeGen/AMDGPU/llvm.amdgcn.mov.dpp.ll
  llvm/trunk/test/CodeGen/AMDGPU/llvm.amdgcn.mqsad.pk.u16.u8.ll
  llvm/trunk/test/CodeGen/AMDGPU/llvm.amdgcn.qsad.pk.u16.u8.ll
  llvm/trunk/test/CodeGen/AMDGPU/loop_break.ll
  llvm/trunk/test/CodeGen/AMDGPU/madak.ll
  llvm/trunk/test/CodeGen/AMDGPU/mubuf-legalize-operands.ll
  llvm/trunk/test/CodeGen/AMDGPU/multilevel-break.ll
  llvm/trunk/test/CodeGen/AMDGPU/select-opt.ll
  llvm/trunk/test/CodeGen/AMDGPU/sgpr-control-flow.ll
  llvm/trunk/test/CodeGen/AMDGPU/si-fix-sgpr-copies.mir
  llvm/trunk/test/CodeGen/AMDGPU/smrd.ll
  llvm/trunk/test/CodeGen/AMDGPU/subreg-coalescer-undef-use.ll
  llvm/trunk/test/CodeGen/AMDGPU/uniform-loop-inside-nonuniform.ll
  llvm/trunk/test/CodeGen/AMDGPU/use-sgpr-multiple-times.ll
  llvm/trunk/test/CodeGen/AMDGPU/valu-i1.ll
  llvm/trunk/test/CodeGen/AMDGPU/vgpr-spill-emergency-stack-slot-compute.ll

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