[llvm] r361493 - [RISCV][NFC] Add nounwind attribute to functions missing it in test/CodeGen/RISCV
Alex Bradbury via llvm-commits
llvm-commits at lists.llvm.org
Thu May 23 05:43:13 PDT 2019
Author: asb
Date: Thu May 23 05:43:13 2019
New Revision: 361493
URL: http://llvm.org/viewvc/llvm-project?rev=361493&view=rev
Log:
[RISCV][NFC] Add nounwind attribute to functions missing it in test/CodeGen/RISCV
r360897 was incomplete, must have applied an old/wip patch. This is in preparation for emitting CFI directives.
Modified:
llvm/trunk/test/CodeGen/RISCV/addc-adde-sube-subc.ll
llvm/trunk/test/CodeGen/RISCV/addcarry.ll
llvm/trunk/test/CodeGen/RISCV/alu64.ll
llvm/trunk/test/CodeGen/RISCV/atomic-cmpxchg-flag.ll
llvm/trunk/test/CodeGen/RISCV/bare-select.ll
llvm/trunk/test/CodeGen/RISCV/branch-relaxation.ll
llvm/trunk/test/CodeGen/RISCV/branch.ll
llvm/trunk/test/CodeGen/RISCV/get-setcc-result-type.ll
llvm/trunk/test/CodeGen/RISCV/hoist-global-addr-base.ll
llvm/trunk/test/CodeGen/RISCV/inline-asm.ll
llvm/trunk/test/CodeGen/RISCV/jumptable.ll
llvm/trunk/test/CodeGen/RISCV/legalize-fneg.ll
llvm/trunk/test/CodeGen/RISCV/rotl-rotr.ll
llvm/trunk/test/CodeGen/RISCV/rv64i-tricky-shifts.ll
llvm/trunk/test/CodeGen/RISCV/select-cc.ll
llvm/trunk/test/CodeGen/RISCV/sext-zext-trunc.ll
llvm/trunk/test/CodeGen/RISCV/tail-calls.ll
llvm/trunk/test/CodeGen/RISCV/zext-with-load-is-free.ll
Modified: llvm/trunk/test/CodeGen/RISCV/addc-adde-sube-subc.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/RISCV/addc-adde-sube-subc.ll?rev=361493&r1=361492&r2=361493&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/RISCV/addc-adde-sube-subc.ll (original)
+++ llvm/trunk/test/CodeGen/RISCV/addc-adde-sube-subc.ll Thu May 23 05:43:13 2019
@@ -4,7 +4,7 @@
; Ensure that the ISDOpcodes ADDC, ADDE, SUBC, SUBE are handled correctly
-define i64 @addc_adde(i64 %a, i64 %b) {
+define i64 @addc_adde(i64 %a, i64 %b) nounwind {
; RV32I-LABEL: addc_adde:
; RV32I: # %bb.0:
; RV32I-NEXT: add a1, a1, a3
@@ -17,7 +17,7 @@ define i64 @addc_adde(i64 %a, i64 %b) {
ret i64 %1
}
-define i64 @subc_sube(i64 %a, i64 %b) {
+define i64 @subc_sube(i64 %a, i64 %b) nounwind {
; RV32I-LABEL: subc_sube:
; RV32I: # %bb.0:
; RV32I-NEXT: sub a1, a1, a3
Modified: llvm/trunk/test/CodeGen/RISCV/addcarry.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/RISCV/addcarry.ll?rev=361493&r1=361492&r2=361493&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/RISCV/addcarry.ll (original)
+++ llvm/trunk/test/CodeGen/RISCV/addcarry.ll Thu May 23 05:43:13 2019
@@ -6,7 +6,7 @@
declare i64 @llvm.smul.fix.i64 (i64, i64, i32)
-define i64 @addcarry(i64 %x, i64 %y) {
+define i64 @addcarry(i64 %x, i64 %y) nounwind {
; RISCV32-LABEL: addcarry:
; RISCV32: # %bb.0:
; RISCV32-NEXT: mul a4, a0, a3
Modified: llvm/trunk/test/CodeGen/RISCV/alu64.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/RISCV/alu64.ll?rev=361493&r1=361492&r2=361493&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/RISCV/alu64.ll (original)
+++ llvm/trunk/test/CodeGen/RISCV/alu64.ll Thu May 23 05:43:13 2019
@@ -375,7 +375,7 @@ define i64 @and(i64 %a, i64 %b) nounwind
; RV64I-only instructions
-define signext i32 @addiw(i32 signext %a) {
+define signext i32 @addiw(i32 signext %a) nounwind {
; RV64I-LABEL: addiw:
; RV64I: # %bb.0:
; RV64I-NEXT: addiw a0, a0, 123
@@ -389,7 +389,7 @@ define signext i32 @addiw(i32 signext %a
ret i32 %1
}
-define signext i32 @slliw(i32 signext %a) {
+define signext i32 @slliw(i32 signext %a) nounwind {
; RV64I-LABEL: slliw:
; RV64I: # %bb.0:
; RV64I-NEXT: slliw a0, a0, 17
@@ -403,7 +403,7 @@ define signext i32 @slliw(i32 signext %a
ret i32 %1
}
-define signext i32 @srliw(i32 %a) {
+define signext i32 @srliw(i32 %a) nounwind {
; RV64I-LABEL: srliw:
; RV64I: # %bb.0:
; RV64I-NEXT: srliw a0, a0, 8
@@ -417,7 +417,7 @@ define signext i32 @srliw(i32 %a) {
ret i32 %1
}
-define signext i32 @sraiw(i32 %a) {
+define signext i32 @sraiw(i32 %a) nounwind {
; RV64I-LABEL: sraiw:
; RV64I: # %bb.0:
; RV64I-NEXT: sraiw a0, a0, 9
@@ -431,7 +431,7 @@ define signext i32 @sraiw(i32 %a) {
ret i32 %1
}
-define signext i32 @sextw(i32 zeroext %a) {
+define signext i32 @sextw(i32 zeroext %a) nounwind {
; RV64I-LABEL: sextw:
; RV64I: # %bb.0:
; RV64I-NEXT: sext.w a0, a0
@@ -443,7 +443,7 @@ define signext i32 @sextw(i32 zeroext %a
ret i32 %a
}
-define signext i32 @addw(i32 signext %a, i32 signext %b) {
+define signext i32 @addw(i32 signext %a, i32 signext %b) nounwind {
; RV64I-LABEL: addw:
; RV64I: # %bb.0:
; RV64I-NEXT: addw a0, a0, a1
@@ -457,7 +457,7 @@ define signext i32 @addw(i32 signext %a,
ret i32 %1
}
-define signext i32 @subw(i32 signext %a, i32 signext %b) {
+define signext i32 @subw(i32 signext %a, i32 signext %b) nounwind {
; RV64I-LABEL: subw:
; RV64I: # %bb.0:
; RV64I-NEXT: subw a0, a0, a1
@@ -471,7 +471,7 @@ define signext i32 @subw(i32 signext %a,
ret i32 %1
}
-define signext i32 @sllw(i32 signext %a, i32 zeroext %b) {
+define signext i32 @sllw(i32 signext %a, i32 zeroext %b) nounwind {
; RV64I-LABEL: sllw:
; RV64I: # %bb.0:
; RV64I-NEXT: sllw a0, a0, a1
@@ -485,7 +485,7 @@ define signext i32 @sllw(i32 signext %a,
ret i32 %1
}
-define signext i32 @srlw(i32 signext %a, i32 zeroext %b) {
+define signext i32 @srlw(i32 signext %a, i32 zeroext %b) nounwind {
; RV64I-LABEL: srlw:
; RV64I: # %bb.0:
; RV64I-NEXT: srlw a0, a0, a1
@@ -499,7 +499,7 @@ define signext i32 @srlw(i32 signext %a,
ret i32 %1
}
-define signext i32 @sraw(i64 %a, i32 zeroext %b) {
+define signext i32 @sraw(i64 %a, i32 zeroext %b) nounwind {
; RV64I-LABEL: sraw:
; RV64I: # %bb.0:
; RV64I-NEXT: sraw a0, a0, a1
Modified: llvm/trunk/test/CodeGen/RISCV/atomic-cmpxchg-flag.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/RISCV/atomic-cmpxchg-flag.ll?rev=361493&r1=361492&r2=361493&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/RISCV/atomic-cmpxchg-flag.ll (original)
+++ llvm/trunk/test/CodeGen/RISCV/atomic-cmpxchg-flag.ll Thu May 23 05:43:13 2019
@@ -7,7 +7,7 @@
; higher bits were masked to zero for the comparison.
define i1 @cmpxchg_i32_seq_cst_seq_cst(i32* %ptr, i32 signext %cmp,
- i32 signext %val) {
+ i32 signext %val) nounwind {
; RV64IA-LABEL: cmpxchg_i32_seq_cst_seq_cst:
; RV64IA: # %bb.0: # %entry
; RV64IA-NEXT: .LBB0_1: # %entry
Modified: llvm/trunk/test/CodeGen/RISCV/bare-select.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/RISCV/bare-select.ll?rev=361493&r1=361492&r2=361493&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/RISCV/bare-select.ll (original)
+++ llvm/trunk/test/CodeGen/RISCV/bare-select.ll Thu May 23 05:43:13 2019
@@ -2,7 +2,7 @@
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV32I
-define i32 @bare_select(i1 %a, i32 %b, i32 %c) {
+define i32 @bare_select(i1 %a, i32 %b, i32 %c) nounwind {
; RV32I-LABEL: bare_select:
; RV32I: # %bb.0:
; RV32I-NEXT: andi a0, a0, 1
@@ -16,7 +16,7 @@ define i32 @bare_select(i1 %a, i32 %b, i
ret i32 %1
}
-define float @bare_select_float(i1 %a, float %b, float %c) {
+define float @bare_select_float(i1 %a, float %b, float %c) nounwind {
; RV32I-LABEL: bare_select_float:
; RV32I: # %bb.0:
; RV32I-NEXT: andi a0, a0, 1
Modified: llvm/trunk/test/CodeGen/RISCV/branch-relaxation.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/RISCV/branch-relaxation.ll?rev=361493&r1=361492&r2=361493&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/RISCV/branch-relaxation.ll (original)
+++ llvm/trunk/test/CodeGen/RISCV/branch-relaxation.ll Thu May 23 05:43:13 2019
@@ -3,7 +3,7 @@
; RUN: -o /dev/null 2>&1
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s | FileCheck %s
-define void @relax_bcc(i1 %a) {
+define void @relax_bcc(i1 %a) nounwind {
; CHECK-LABEL: relax_bcc:
; CHECK: # %bb.0:
; CHECK-NEXT: andi a0, a0, 1
@@ -25,7 +25,7 @@ tail:
ret void
}
-define i32 @relax_jal(i1 %a) {
+define i32 @relax_jal(i1 %a) nounwind {
; CHECK-LABEL: relax_jal:
; CHECK: # %bb.0:
; CHECK-NEXT: andi a0, a0, 1
Modified: llvm/trunk/test/CodeGen/RISCV/branch.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/RISCV/branch.ll?rev=361493&r1=361492&r2=361493&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/RISCV/branch.ll (original)
+++ llvm/trunk/test/CodeGen/RISCV/branch.ll Thu May 23 05:43:13 2019
@@ -2,7 +2,7 @@
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32I %s
-define void @foo(i32 %a, i32 *%b, i1 %c) {
+define void @foo(i32 %a, i32 *%b, i1 %c) nounwind {
; RV32I-LABEL: foo:
; RV32I: # %bb.0:
; RV32I-NEXT: lw a3, 0(a1)
Modified: llvm/trunk/test/CodeGen/RISCV/get-setcc-result-type.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/RISCV/get-setcc-result-type.ll?rev=361493&r1=361492&r2=361493&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/RISCV/get-setcc-result-type.ll (original)
+++ llvm/trunk/test/CodeGen/RISCV/get-setcc-result-type.ll Thu May 23 05:43:13 2019
@@ -2,7 +2,7 @@
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32I %s
-define void @getSetCCResultType(<4 x i32>* %p, <4 x i32>* %q) {
+define void @getSetCCResultType(<4 x i32>* %p, <4 x i32>* %q) nounwind {
; RV32I-LABEL: getSetCCResultType:
; RV32I: # %bb.0: # %entry
; RV32I-NEXT: lw a1, 12(a0)
Modified: llvm/trunk/test/CodeGen/RISCV/hoist-global-addr-base.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/RISCV/hoist-global-addr-base.ll?rev=361493&r1=361492&r2=361493&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/RISCV/hoist-global-addr-base.ll (original)
+++ llvm/trunk/test/CodeGen/RISCV/hoist-global-addr-base.ll Thu May 23 05:43:13 2019
@@ -7,7 +7,7 @@
@g = global [1048576 x i8] zeroinitializer, align 1
-define dso_local void @multiple_stores() local_unnamed_addr {
+define dso_local void @multiple_stores() local_unnamed_addr nounwind {
; CHECK-LABEL: multiple_stores:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lui a0, %hi(s)
@@ -23,7 +23,7 @@ entry:
ret void
}
-define dso_local void @control_flow_with_mem_access() local_unnamed_addr #0 {
+define dso_local void @control_flow_with_mem_access() local_unnamed_addr nounwind {
; CHECK-LABEL: control_flow_with_mem_access:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lui a0, %hi(s)
@@ -57,7 +57,7 @@ if.end:
; lui a0, 18 ---> offset
; addi a0, a0, -160
; add a0, a0, a1 ---> base + offset.
-define i8* @big_offset_neg_addi() {
+define i8* @big_offset_neg_addi() nounwind {
; CHECK-LABEL: big_offset_neg_addi:
; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, %hi(g+73568)
@@ -72,7 +72,7 @@ define i8* @big_offset_neg_addi() {
; addi a0, a0, %lo(g)
; lui a1, 128 ---> offset
; add a0, a0, a1 ---> base + offset.
-define i8* @big_offset_lui_tail() {
+define i8* @big_offset_lui_tail() nounwind {
; CHECK-LABEL: big_offset_lui_tail:
; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, %hi(g+524288)
@@ -81,7 +81,7 @@ define i8* @big_offset_lui_tail() {
ret i8* getelementptr inbounds ([1048576 x i8], [1048576 x i8]* @g, i32 0, i32 524288)
}
-define dso_local i32* @big_offset_one_use() local_unnamed_addr {
+define dso_local i32* @big_offset_one_use() local_unnamed_addr nounwind {
; CHECK-LABEL: big_offset_one_use:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lui a0, %hi(s+16572)
@@ -91,7 +91,7 @@ entry:
ret i32* getelementptr inbounds (%struct.S, %struct.S* @s, i32 0, i32 5)
}
-define dso_local i32* @small_offset_one_use() local_unnamed_addr {
+define dso_local i32* @small_offset_one_use() local_unnamed_addr nounwind {
; CHECK-LABEL: small_offset_one_use:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lui a0, %hi(s+160)
@@ -101,8 +101,7 @@ entry:
ret i32* getelementptr inbounds (%struct.S, %struct.S* @s, i32 0, i32 1)
}
-; Function Attrs: norecurse nounwind optsize readonly
-define dso_local i32* @control_flow_no_mem(i32 %n) local_unnamed_addr #1 {
+define dso_local i32* @control_flow_no_mem(i32 %n) local_unnamed_addr nounwind {
; CHECK-LABEL: control_flow_no_mem:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lui a0, %hi(s)
@@ -156,7 +155,7 @@ if.end:
declare void @abort()
-define dso_local void @one_store() local_unnamed_addr {
+define dso_local void @one_store() local_unnamed_addr nounwind {
; CHECK-LABEL: one_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lui a0, %hi(s+160)
Modified: llvm/trunk/test/CodeGen/RISCV/inline-asm.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/RISCV/inline-asm.ll?rev=361493&r1=361492&r2=361493&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/RISCV/inline-asm.ll (original)
+++ llvm/trunk/test/CodeGen/RISCV/inline-asm.ll Thu May 23 05:43:13 2019
@@ -6,7 +6,7 @@
@gi = external global i32
-define i32 @constraint_r(i32 %a) {
+define i32 @constraint_r(i32 %a) nounwind {
; RV32I-LABEL: constraint_r:
; RV32I: # %bb.0:
; RV32I-NEXT: lui a1, %hi(gi)
@@ -29,7 +29,7 @@ define i32 @constraint_r(i32 %a) {
ret i32 %2
}
-define i32 @constraint_i(i32 %a) {
+define i32 @constraint_i(i32 %a) nounwind {
; RV32I-LABEL: constraint_i:
; RV32I: # %bb.0:
; RV32I-NEXT: #APP
@@ -48,7 +48,7 @@ define i32 @constraint_i(i32 %a) {
ret i32 %2
}
-define void @constraint_m(i32* %a) {
+define void @constraint_m(i32* %a) nounwind {
; RV32I-LABEL: constraint_m:
; RV32I: # %bb.0:
; RV32I-NEXT: #APP
@@ -64,7 +64,7 @@ define void @constraint_m(i32* %a) {
ret void
}
-define i32 @constraint_m2(i32* %a) {
+define i32 @constraint_m2(i32* %a) nounwind {
; RV32I-LABEL: constraint_m2:
; RV32I: # %bb.0:
; RV32I-NEXT: #APP
Modified: llvm/trunk/test/CodeGen/RISCV/jumptable.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/RISCV/jumptable.ll?rev=361493&r1=361492&r2=361493&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/RISCV/jumptable.ll (original)
+++ llvm/trunk/test/CodeGen/RISCV/jumptable.ll Thu May 23 05:43:13 2019
@@ -2,7 +2,7 @@
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV32I
-define void @jt(i32 %in, i32* %out) {
+define void @jt(i32 %in, i32* %out) nounwind {
; RV32I-LABEL: jt:
; RV32I: # %bb.0: # %entry
; RV32I-NEXT: addi a2, zero, 2
Modified: llvm/trunk/test/CodeGen/RISCV/legalize-fneg.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/RISCV/legalize-fneg.ll?rev=361493&r1=361492&r2=361493&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/RISCV/legalize-fneg.ll (original)
+++ llvm/trunk/test/CodeGen/RISCV/legalize-fneg.ll Thu May 23 05:43:13 2019
@@ -4,7 +4,7 @@
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64 %s
-define void @test1(float* %a, float* %b) {
+define void @test1(float* %a, float* %b) nounwind {
; RV32-LABEL: test1:
; RV32: # %bb.0: # %entry
; RV32-NEXT: lw a1, 0(a1)
@@ -28,7 +28,7 @@ entry:
ret void
}
-define void @test2(double* %a, double* %b) {
+define void @test2(double* %a, double* %b) nounwind {
; RV32-LABEL: test2:
; RV32: # %bb.0: # %entry
; RV32-NEXT: lw a2, 4(a1)
@@ -54,7 +54,7 @@ entry:
ret void
}
-define void @test3(fp128* %a, fp128* %b) {
+define void @test3(fp128* %a, fp128* %b) nounwind {
; RV32-LABEL: test3:
; RV32: # %bb.0: # %entry
; RV32-NEXT: lw a2, 12(a1)
Modified: llvm/trunk/test/CodeGen/RISCV/rotl-rotr.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/RISCV/rotl-rotr.ll?rev=361493&r1=361492&r2=361493&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/RISCV/rotl-rotr.ll (original)
+++ llvm/trunk/test/CodeGen/RISCV/rotl-rotr.ll Thu May 23 05:43:13 2019
@@ -5,7 +5,7 @@
; These IR sequences will generate ISD::ROTL and ISD::ROTR nodes, that the
; RISC-V backend must be able to select
-define i32 @rotl(i32 %x, i32 %y) {
+define i32 @rotl(i32 %x, i32 %y) nounwind {
; RV32I-LABEL: rotl:
; RV32I: # %bb.0:
; RV32I-NEXT: addi a2, zero, 32
@@ -21,7 +21,7 @@ define i32 @rotl(i32 %x, i32 %y) {
ret i32 %d
}
-define i32 @rotr(i32 %x, i32 %y) {
+define i32 @rotr(i32 %x, i32 %y) nounwind {
; RV32I-LABEL: rotr:
; RV32I: # %bb.0:
; RV32I-NEXT: addi a2, zero, 32
Modified: llvm/trunk/test/CodeGen/RISCV/rv64i-tricky-shifts.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/RISCV/rv64i-tricky-shifts.ll?rev=361493&r1=361492&r2=361493&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/RISCV/rv64i-tricky-shifts.ll (original)
+++ llvm/trunk/test/CodeGen/RISCV/rv64i-tricky-shifts.ll Thu May 23 05:43:13 2019
@@ -7,7 +7,7 @@
; patterns might make the mistake of assuming that a (sext_inreg foo, i32) can
; only be produced when sign-extending an i32 type.
-define i64 @tricky_shl(i64 %a, i64 %b) {
+define i64 @tricky_shl(i64 %a, i64 %b) nounwind {
; RV64I-LABEL: tricky_shl:
; RV64I: # %bb.0:
; RV64I-NEXT: sll a0, a0, a1
@@ -19,7 +19,7 @@ define i64 @tricky_shl(i64 %a, i64 %b) {
ret i64 %3
}
-define i64 @tricky_lshr(i64 %a, i64 %b) {
+define i64 @tricky_lshr(i64 %a, i64 %b) nounwind {
; RV64I-LABEL: tricky_lshr:
; RV64I: # %bb.0:
; RV64I-NEXT: slli a0, a0, 32
@@ -31,7 +31,7 @@ define i64 @tricky_lshr(i64 %a, i64 %b)
ret i64 %2
}
-define i64 @tricky_ashr(i64 %a, i64 %b) {
+define i64 @tricky_ashr(i64 %a, i64 %b) nounwind {
; RV64I-LABEL: tricky_ashr:
; RV64I: # %bb.0:
; RV64I-NEXT: sext.w a0, a0
Modified: llvm/trunk/test/CodeGen/RISCV/select-cc.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/RISCV/select-cc.ll?rev=361493&r1=361492&r2=361493&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/RISCV/select-cc.ll (original)
+++ llvm/trunk/test/CodeGen/RISCV/select-cc.ll Thu May 23 05:43:13 2019
@@ -2,7 +2,7 @@
; RUN: llc -mtriple=riscv32 -disable-block-placement -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32I %s
-define i32 @foo(i32 %a, i32 *%b) {
+define i32 @foo(i32 %a, i32 *%b) nounwind {
; RV32I-LABEL: foo:
; RV32I: # %bb.0:
; RV32I-NEXT: lw a2, 0(a1)
Modified: llvm/trunk/test/CodeGen/RISCV/sext-zext-trunc.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/RISCV/sext-zext-trunc.ll?rev=361493&r1=361492&r2=361493&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/RISCV/sext-zext-trunc.ll (original)
+++ llvm/trunk/test/CodeGen/RISCV/sext-zext-trunc.ll Thu May 23 05:43:13 2019
@@ -4,7 +4,7 @@
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV64I
-define i8 @sext_i1_to_i8(i1 %a) {
+define i8 @sext_i1_to_i8(i1 %a) nounwind {
; RV32I-LABEL: sext_i1_to_i8:
; RV32I: # %bb.0:
; RV32I-NEXT: andi a0, a0, 1
@@ -20,7 +20,7 @@ define i8 @sext_i1_to_i8(i1 %a) {
ret i8 %1
}
-define i16 @sext_i1_to_i16(i1 %a) {
+define i16 @sext_i1_to_i16(i1 %a) nounwind {
; RV32I-LABEL: sext_i1_to_i16:
; RV32I: # %bb.0:
; RV32I-NEXT: andi a0, a0, 1
@@ -36,7 +36,7 @@ define i16 @sext_i1_to_i16(i1 %a) {
ret i16 %1
}
-define i32 @sext_i1_to_i32(i1 %a) {
+define i32 @sext_i1_to_i32(i1 %a) nounwind {
; RV32I-LABEL: sext_i1_to_i32:
; RV32I: # %bb.0:
; RV32I-NEXT: andi a0, a0, 1
@@ -52,7 +52,7 @@ define i32 @sext_i1_to_i32(i1 %a) {
ret i32 %1
}
-define i64 @sext_i1_to_i64(i1 %a) {
+define i64 @sext_i1_to_i64(i1 %a) nounwind {
; RV32I-LABEL: sext_i1_to_i64:
; RV32I: # %bb.0:
; RV32I-NEXT: andi a0, a0, 1
@@ -69,7 +69,7 @@ define i64 @sext_i1_to_i64(i1 %a) {
ret i64 %1
}
-define i16 @sext_i8_to_i16(i8 %a) {
+define i16 @sext_i8_to_i16(i8 %a) nounwind {
; RV32I-LABEL: sext_i8_to_i16:
; RV32I: # %bb.0:
; RV32I-NEXT: slli a0, a0, 24
@@ -85,7 +85,7 @@ define i16 @sext_i8_to_i16(i8 %a) {
ret i16 %1
}
-define i32 @sext_i8_to_i32(i8 %a) {
+define i32 @sext_i8_to_i32(i8 %a) nounwind {
; RV32I-LABEL: sext_i8_to_i32:
; RV32I: # %bb.0:
; RV32I-NEXT: slli a0, a0, 24
@@ -101,7 +101,7 @@ define i32 @sext_i8_to_i32(i8 %a) {
ret i32 %1
}
-define i64 @sext_i8_to_i64(i8 %a) {
+define i64 @sext_i8_to_i64(i8 %a) nounwind {
; RV32I-LABEL: sext_i8_to_i64:
; RV32I: # %bb.0:
; RV32I-NEXT: slli a1, a0, 24
@@ -118,7 +118,7 @@ define i64 @sext_i8_to_i64(i8 %a) {
ret i64 %1
}
-define i32 @sext_i16_to_i32(i16 %a) {
+define i32 @sext_i16_to_i32(i16 %a) nounwind {
; RV32I-LABEL: sext_i16_to_i32:
; RV32I: # %bb.0:
; RV32I-NEXT: slli a0, a0, 16
@@ -134,7 +134,7 @@ define i32 @sext_i16_to_i32(i16 %a) {
ret i32 %1
}
-define i64 @sext_i16_to_i64(i16 %a) {
+define i64 @sext_i16_to_i64(i16 %a) nounwind {
; RV32I-LABEL: sext_i16_to_i64:
; RV32I: # %bb.0:
; RV32I-NEXT: slli a1, a0, 16
@@ -151,7 +151,7 @@ define i64 @sext_i16_to_i64(i16 %a) {
ret i64 %1
}
-define i64 @sext_i32_to_i64(i32 %a) {
+define i64 @sext_i32_to_i64(i32 %a) nounwind {
; RV32I-LABEL: sext_i32_to_i64:
; RV32I: # %bb.0:
; RV32I-NEXT: srai a1, a0, 31
@@ -165,7 +165,7 @@ define i64 @sext_i32_to_i64(i32 %a) {
ret i64 %1
}
-define i8 @zext_i1_to_i8(i1 %a) {
+define i8 @zext_i1_to_i8(i1 %a) nounwind {
; RV32I-LABEL: zext_i1_to_i8:
; RV32I: # %bb.0:
; RV32I-NEXT: andi a0, a0, 1
@@ -179,7 +179,7 @@ define i8 @zext_i1_to_i8(i1 %a) {
ret i8 %1
}
-define i16 @zext_i1_to_i16(i1 %a) {
+define i16 @zext_i1_to_i16(i1 %a) nounwind {
; RV32I-LABEL: zext_i1_to_i16:
; RV32I: # %bb.0:
; RV32I-NEXT: andi a0, a0, 1
@@ -193,7 +193,7 @@ define i16 @zext_i1_to_i16(i1 %a) {
ret i16 %1
}
-define i32 @zext_i1_to_i32(i1 %a) {
+define i32 @zext_i1_to_i32(i1 %a) nounwind {
; RV32I-LABEL: zext_i1_to_i32:
; RV32I: # %bb.0:
; RV32I-NEXT: andi a0, a0, 1
@@ -207,7 +207,7 @@ define i32 @zext_i1_to_i32(i1 %a) {
ret i32 %1
}
-define i64 @zext_i1_to_i64(i1 %a) {
+define i64 @zext_i1_to_i64(i1 %a) nounwind {
; RV32I-LABEL: zext_i1_to_i64:
; RV32I: # %bb.0:
; RV32I-NEXT: andi a0, a0, 1
@@ -222,7 +222,7 @@ define i64 @zext_i1_to_i64(i1 %a) {
ret i64 %1
}
-define i16 @zext_i8_to_i16(i8 %a) {
+define i16 @zext_i8_to_i16(i8 %a) nounwind {
; RV32I-LABEL: zext_i8_to_i16:
; RV32I: # %bb.0:
; RV32I-NEXT: andi a0, a0, 255
@@ -236,7 +236,7 @@ define i16 @zext_i8_to_i16(i8 %a) {
ret i16 %1
}
-define i32 @zext_i8_to_i32(i8 %a) {
+define i32 @zext_i8_to_i32(i8 %a) nounwind {
; RV32I-LABEL: zext_i8_to_i32:
; RV32I: # %bb.0:
; RV32I-NEXT: andi a0, a0, 255
@@ -250,7 +250,7 @@ define i32 @zext_i8_to_i32(i8 %a) {
ret i32 %1
}
-define i64 @zext_i8_to_i64(i8 %a) {
+define i64 @zext_i8_to_i64(i8 %a) nounwind {
; RV32I-LABEL: zext_i8_to_i64:
; RV32I: # %bb.0:
; RV32I-NEXT: andi a0, a0, 255
@@ -265,7 +265,7 @@ define i64 @zext_i8_to_i64(i8 %a) {
ret i64 %1
}
-define i32 @zext_i16_to_i32(i16 %a) {
+define i32 @zext_i16_to_i32(i16 %a) nounwind {
; RV32I-LABEL: zext_i16_to_i32:
; RV32I: # %bb.0:
; RV32I-NEXT: lui a1, 16
@@ -283,7 +283,7 @@ define i32 @zext_i16_to_i32(i16 %a) {
ret i32 %1
}
-define i64 @zext_i16_to_i64(i16 %a) {
+define i64 @zext_i16_to_i64(i16 %a) nounwind {
; RV32I-LABEL: zext_i16_to_i64:
; RV32I: # %bb.0:
; RV32I-NEXT: lui a1, 16
@@ -302,7 +302,7 @@ define i64 @zext_i16_to_i64(i16 %a) {
ret i64 %1
}
-define i64 @zext_i32_to_i64(i32 %a) {
+define i64 @zext_i32_to_i64(i32 %a) nounwind {
; RV32I-LABEL: zext_i32_to_i64:
; RV32I: # %bb.0:
; RV32I-NEXT: mv a1, zero
@@ -317,7 +317,7 @@ define i64 @zext_i32_to_i64(i32 %a) {
ret i64 %1
}
-define i1 @trunc_i8_to_i1(i8 %a) {
+define i1 @trunc_i8_to_i1(i8 %a) nounwind {
; RV32I-LABEL: trunc_i8_to_i1:
; RV32I: # %bb.0:
; RV32I-NEXT: ret
@@ -329,7 +329,7 @@ define i1 @trunc_i8_to_i1(i8 %a) {
ret i1 %1
}
-define i1 @trunc_i16_to_i1(i16 %a) {
+define i1 @trunc_i16_to_i1(i16 %a) nounwind {
; RV32I-LABEL: trunc_i16_to_i1:
; RV32I: # %bb.0:
; RV32I-NEXT: ret
@@ -341,7 +341,7 @@ define i1 @trunc_i16_to_i1(i16 %a) {
ret i1 %1
}
-define i1 @trunc_i32_to_i1(i32 %a) {
+define i1 @trunc_i32_to_i1(i32 %a) nounwind {
; RV32I-LABEL: trunc_i32_to_i1:
; RV32I: # %bb.0:
; RV32I-NEXT: ret
@@ -353,7 +353,7 @@ define i1 @trunc_i32_to_i1(i32 %a) {
ret i1 %1
}
-define i1 @trunc_i64_to_i1(i64 %a) {
+define i1 @trunc_i64_to_i1(i64 %a) nounwind {
; RV32I-LABEL: trunc_i64_to_i1:
; RV32I: # %bb.0:
; RV32I-NEXT: ret
@@ -365,7 +365,7 @@ define i1 @trunc_i64_to_i1(i64 %a) {
ret i1 %1
}
-define i8 @trunc_i16_to_i8(i16 %a) {
+define i8 @trunc_i16_to_i8(i16 %a) nounwind {
; RV32I-LABEL: trunc_i16_to_i8:
; RV32I: # %bb.0:
; RV32I-NEXT: ret
@@ -377,7 +377,7 @@ define i8 @trunc_i16_to_i8(i16 %a) {
ret i8 %1
}
-define i8 @trunc_i32_to_i8(i32 %a) {
+define i8 @trunc_i32_to_i8(i32 %a) nounwind {
; RV32I-LABEL: trunc_i32_to_i8:
; RV32I: # %bb.0:
; RV32I-NEXT: ret
@@ -389,7 +389,7 @@ define i8 @trunc_i32_to_i8(i32 %a) {
ret i8 %1
}
-define i8 @trunc_i64_to_i8(i64 %a) {
+define i8 @trunc_i64_to_i8(i64 %a) nounwind {
; RV32I-LABEL: trunc_i64_to_i8:
; RV32I: # %bb.0:
; RV32I-NEXT: ret
@@ -401,7 +401,7 @@ define i8 @trunc_i64_to_i8(i64 %a) {
ret i8 %1
}
-define i16 @trunc_i32_to_i16(i32 %a) {
+define i16 @trunc_i32_to_i16(i32 %a) nounwind {
; RV32I-LABEL: trunc_i32_to_i16:
; RV32I: # %bb.0:
; RV32I-NEXT: ret
@@ -413,7 +413,7 @@ define i16 @trunc_i32_to_i16(i32 %a) {
ret i16 %1
}
-define i16 @trunc_i64_to_i16(i64 %a) {
+define i16 @trunc_i64_to_i16(i64 %a) nounwind {
; RV32I-LABEL: trunc_i64_to_i16:
; RV32I: # %bb.0:
; RV32I-NEXT: ret
@@ -425,7 +425,7 @@ define i16 @trunc_i64_to_i16(i64 %a) {
ret i16 %1
}
-define i32 @trunc_i64_to_i32(i64 %a) {
+define i32 @trunc_i64_to_i32(i64 %a) nounwind {
; RV32I-LABEL: trunc_i64_to_i32:
; RV32I: # %bb.0:
; RV32I-NEXT: ret
Modified: llvm/trunk/test/CodeGen/RISCV/tail-calls.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/RISCV/tail-calls.ll?rev=361493&r1=361492&r2=361493&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/RISCV/tail-calls.ll (original)
+++ llvm/trunk/test/CodeGen/RISCV/tail-calls.ll Thu May 23 05:43:13 2019
@@ -3,7 +3,7 @@
; Perform tail call optimization for global address.
declare i32 @callee_tail(i32 %i)
-define i32 @caller_tail(i32 %i) {
+define i32 @caller_tail(i32 %i) nounwind {
; CHECK-LABEL: caller_tail
; CHECK: tail callee_tail
entry:
@@ -26,7 +26,7 @@ entry:
; Perform indirect tail call optimization (for function pointer call).
declare void @callee_indirect1()
declare void @callee_indirect2()
-define void @caller_indirect_tail(i32 %a) {
+define void @caller_indirect_tail(i32 %a) nounwind {
; CHECK-LABEL: caller_indirect_tail
; CHECK-NOT: call callee_indirect1
; CHECK-NOT: call callee_indirect2
@@ -49,7 +49,7 @@ entry:
; Do not tail call optimize functions with varargs.
declare i32 @callee_varargs(i32, ...)
-define void @caller_varargs(i32 %a, i32 %b) {
+define void @caller_varargs(i32 %a, i32 %b) nounwind {
; CHECK-LABEL: caller_varargs
; CHECK-NOT: tail callee_varargs
; CHECK: call callee_varargs
@@ -60,7 +60,7 @@ entry:
; Do not tail call optimize if stack is used to pass parameters.
declare i32 @callee_args(i32 %a, i32 %b, i32 %c, i32 %dd, i32 %e, i32 %ff, i32 %g, i32 %h, i32 %i, i32 %j, i32 %k, i32 %l, i32 %m, i32 %n)
-define i32 @caller_args(i32 %a, i32 %b, i32 %c, i32 %dd, i32 %e, i32 %ff, i32 %g, i32 %h, i32 %i, i32 %j, i32 %k, i32 %l, i32 %m, i32 %n) {
+define i32 @caller_args(i32 %a, i32 %b, i32 %c, i32 %dd, i32 %e, i32 %ff, i32 %g, i32 %h, i32 %i, i32 %j, i32 %k, i32 %l, i32 %m, i32 %n) nounwind {
; CHECK-LABEL: caller_args
; CHECK-NOT: tail callee_args
; CHECK: call callee_args
@@ -71,7 +71,7 @@ entry:
; Do not tail call optimize if parameters need to be passed indirectly.
declare i32 @callee_indirect_args(fp128 %a)
-define void @caller_indirect_args() {
+define void @caller_indirect_args() nounwind {
; CHECK-LABEL: caller_indirect_args
; CHECK-NOT: tail callee_indirect_args
; CHECK: call callee_indirect_args
@@ -85,7 +85,7 @@ entry:
; calls) is implementation-defined, so we cannot rely on the linker replacing
; the tail call with a return.
declare extern_weak void @callee_weak()
-define void @caller_weak() {
+define void @caller_weak() nounwind {
; CHECK-LABEL: caller_weak
; CHECK-NOT: tail callee_weak
; CHECK: call callee_weak
@@ -112,7 +112,7 @@ attributes #0 = { "interrupt"="machine"
; we want to reuse during a tail call. Do not tail call optimize functions with
; byval parameters.
declare i32 @callee_byval(i32** byval %a)
-define i32 @caller_byval() {
+define i32 @caller_byval() nounwind {
; CHECK-LABEL: caller_byval
; CHECK-NOT: tail callee_byval
; CHECK: call callee_byval
@@ -127,7 +127,7 @@ entry:
@a = global %struct.A zeroinitializer
declare void @callee_struct(%struct.A* sret %a)
-define void @caller_nostruct() {
+define void @caller_nostruct() nounwind {
; CHECK-LABEL: caller_nostruct
; CHECK-NOT: tail callee_struct
; CHECK: call callee_struct
@@ -138,7 +138,7 @@ entry:
; Do not tail call optimize if caller uses structret semantics.
declare void @callee_nostruct()
-define void @caller_struct(%struct.A* sret %a) {
+define void @caller_struct(%struct.A* sret %a) nounwind {
; CHECK-LABEL: caller_struct
; CHECK-NOT: tail callee_nostruct
; CHECK: call callee_nostruct
Modified: llvm/trunk/test/CodeGen/RISCV/zext-with-load-is-free.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/RISCV/zext-with-load-is-free.ll?rev=361493&r1=361492&r2=361493&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/RISCV/zext-with-load-is-free.ll (original)
+++ llvm/trunk/test/CodeGen/RISCV/zext-with-load-is-free.ll Thu May 23 05:43:13 2019
@@ -6,7 +6,7 @@
@bytes = global [5 x i8] zeroinitializer, align 1
-define i32 @test_zext_i8() {
+define i32 @test_zext_i8() nounwind {
; RV32I-LABEL: test_zext_i8:
; RV32I: # %bb.0: # %entry
; RV32I-NEXT: lui a0, %hi(bytes)
@@ -41,7 +41,7 @@ if.end:
@shorts = global [5 x i16] zeroinitializer, align 2
-define i32 @test_zext_i16() {
+define i32 @test_zext_i16() nounwind {
; RV32I-LABEL: test_zext_i16:
; RV32I: # %bb.0: # %entry
; RV32I-NEXT: lui a0, %hi(shorts)
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