[PATCH] D62301: Fold Address Computations into Load/Store instructions for AArch64

[Ramakota Reddy via Phabricator via llvm-commits]

ramred01 created this revision.
ramred01 added reviewers: t.p.northover, evandro.
Herald added subscribers: kristof.beyls, javed.absar.

When compiling with -Oz, the indexed or offset address computations with or without scaling for Load/Store instructions is not folding into the Load/Store instructions for AArch64 even when the AArch64 ISA has load/store instructions with addressing modes that allow for indexed/offset addresses with/without scaling.

This has been fixed by identifying the load/store instructions and then scanning backwards for the ADD/SUB instructions that perform the address computation for the load/store instructions.  Thereafter, we replace the ADD/SUB and the Load/Store instruction with an appropriate Load/Store instruction, which has the address computation folded in.


https://reviews.llvm.org/D62301

Files:
  include/llvm/CodeGen/MachineOperand.h
  lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
  test/CodeGen/AArch64/fold_addressing_modes_aarch64.ll

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