[compiler-rt] r361423 - [X86] Add more icelake model numbers to compiler-rt implementation of __builtin_cpu_is.

[Craig Topper via llvm-commits]

Author: ctopper
Date: Wed May 22 12:51:48 2019
New Revision: 361423

URL: http://llvm.org/viewvc/llvm-project?rev=361423&view=rev
Log:
[X86] Add more icelake model numbers to compiler-rt implementation of __builtin_cpu_is.

Using model numbers found in Table 2-1 of the May 2019 version
of the Intel Software Developer's Manual Volume 4.

Modified:
    compiler-rt/trunk/lib/builtins/cpu_model.c

Modified: compiler-rt/trunk/lib/builtins/cpu_model.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/builtins/cpu_model.c?rev=361423&r1=361422&r2=361423&view=diff
==============================================================================
--- compiler-rt/trunk/lib/builtins/cpu_model.c (original)
+++ compiler-rt/trunk/lib/builtins/cpu_model.c Wed May 22 12:51:48 2019
@@ -363,11 +363,19 @@ static void getIntelProcessorTypeAndSubt
       break;
 
     // Icelake:
+    case 0x7d:
     case 0x7e:
       *Type = INTEL_COREI7;
       *Subtype = INTEL_COREI7_ICELAKE_CLIENT; // "icelake-client"
       break;
 
+    // Icelake Xeon:
+    case 0x6a:
+    case 0x6c:
+      *Type = INTEL_COREI7;
+      *Subtype = INTEL_COREI7_ICELAKE_SERVER; // "icelake-server"
+      break;
+
     case 0x1c: // Most 45 nm Intel Atom processors
     case 0x26: // 45 nm Atom Lincroft
     case 0x27: // 32 nm Atom Medfield