[llvm] r361375 - [Hexagon] assert getRegisterBitWidth returns non-zero value. NFCI.

[Simon Pilgrim via llvm-commits]

Author: rksimon
Date: Wed May 22 05:25:46 2019
New Revision: 361375

URL: http://llvm.org/viewvc/llvm-project?rev=361375&view=rev
Log:
[Hexagon] assert getRegisterBitWidth returns non-zero value. NFCI.

Fixes scan-build warning.

Modified:
    llvm/trunk/lib/Target/Hexagon/HexagonTargetTransformInfo.cpp

Modified: llvm/trunk/lib/Target/Hexagon/HexagonTargetTransformInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonTargetTransformInfo.cpp?rev=361375&r1=361374&r2=361375&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonTargetTransformInfo.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonTargetTransformInfo.cpp Wed May 22 05:25:46 2019
@@ -160,14 +160,15 @@ unsigned HexagonTTIImpl::getMemoryOpCost
     unsigned VecWidth = VecTy->getBitWidth();
     if (useHVX() && isTypeForHVX(VecTy)) {
       unsigned RegWidth = getRegisterBitWidth(true);
-      Alignment = std::min(Alignment, RegWidth/8);
+      assert(RegWidth && "Non-zero vector register width expected");
       // Cost of HVX loads.
       if (VecWidth % RegWidth == 0)
         return VecWidth / RegWidth;
       // Cost of constructing HVX vector from scalar loads.
+      Alignment = std::min(Alignment, RegWidth / 8);
       unsigned AlignWidth = 8 * std::max(1u, Alignment);
       unsigned NumLoads = alignTo(VecWidth, AlignWidth) / AlignWidth;
-      return 3*NumLoads;
+      return 3 * NumLoads;
     }
 
     // Non-HVX vectors.