[PATCH] D62194: AMDGPU: Fix not marking new gfx10 SGPRs as CSRs

[Matt Arsenault via Phabricator via llvm-commits]

arsenm created this revision.
arsenm added a reviewer: rampitec.
Herald added subscribers: t-tye, tpr, dstuttard, yaxunl, nhaehnle, wdng, jvesely, kzhuravl.

https://reviews.llvm.org/D62194

Files:
  lib/Target/AMDGPU/AMDGPUCallingConv.td
  test/CodeGen/AMDGPU/csr-gfx10.ll


Index: test/CodeGen/AMDGPU/csr-gfx10.ll
===================================================================
--- /dev/null
+++ test/CodeGen/AMDGPU/csr-gfx10.ll
@@ -0,0 +1,15 @@
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -o - %s | FileCheck -check-prefix=GFX10 %s
+
+; Make sure new higher SGPRs are callee saved
+; GFX10-LABEL: {{^}}callee_new_sgprs:
+; GFX10: v_writelane_b32 v0, s104, 0
+; GFX10: v_writelane_b32 v0, s105, 1
+; GFX10: ; clobber s104
+; GFX10: ; clobber s105
+; GFX10: v_readlane_b32 s105, v0, 1
+; GFX10: v_readlane_b32 s104, v0, 0
+define void @callee_new_sgprs() {
+  call void asm sideeffect "; clobber s104", "~{s104}"()
+  call void asm sideeffect "; clobber s105", "~{s105}"()
+  ret void
+}
Index: lib/Target/AMDGPU/AMDGPUCallingConv.td
===================================================================
--- lib/Target/AMDGPU/AMDGPUCallingConv.td
+++ lib/Target/AMDGPU/AMDGPUCallingConv.td
@@ -110,12 +110,12 @@
   (sequence "VGPR%u", 32, 255)
 >;
 
-def CSR_AMDGPU_SGPRs_32_103 : CalleeSavedRegs<
-  (sequence "SGPR%u", 32, 103)
+def CSR_AMDGPU_SGPRs_32_105 : CalleeSavedRegs<
+  (sequence "SGPR%u", 32, 105)
 >;
 
 def CSR_AMDGPU_HighRegs : CalleeSavedRegs<
-  (add CSR_AMDGPU_VGPRs_32_255, CSR_AMDGPU_SGPRs_32_103)
+  (add CSR_AMDGPU_VGPRs_32_255, CSR_AMDGPU_SGPRs_32_105)
 >;
 
 // Calling convention for leaf functions


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