[PATCH] D62108: [AArch64] Handle lowering lround on windows, where long is 32 bit
Martin Storsjö via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Mon May 20 12:53:43 PDT 2019
This revision was automatically updated to reflect the committed changes.
Closed by commit rL361192: [AArch64] Handle lowering lround on windows, where long is 32 bit (authored by mstorsjo, committed by ).
Changed prior to commit:
https://reviews.llvm.org/D62108?vs=200184&id=200350#toc
Repository:
rL LLVM
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D62108/new/
https://reviews.llvm.org/D62108
Files:
llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td
llvm/trunk/test/CodeGen/AArch64/lround-conv-win.ll
Index: llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td
===================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td
+++ llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td
@@ -3083,6 +3083,10 @@
defm : FPToIntegerPats<fp_to_sint, fround, "FCVTAS">;
defm : FPToIntegerPats<fp_to_uint, fround, "FCVTAU">;
+def : Pat<(i32 (lround f32:$Rn)),
+ (!cast<Instruction>(FCVTASUWSr) f32:$Rn)>;
+def : Pat<(i32 (lround f64:$Rn)),
+ (!cast<Instruction>(FCVTASUWDr) f64:$Rn)>;
def : Pat<(i64 (lround f32:$Rn)),
(!cast<Instruction>(FCVTASUXSr) f32:$Rn)>;
def : Pat<(i64 (lround f64:$Rn)),
Index: llvm/trunk/test/CodeGen/AArch64/lround-conv-win.ll
===================================================================
--- llvm/trunk/test/CodeGen/AArch64/lround-conv-win.ll
+++ llvm/trunk/test/CodeGen/AArch64/lround-conv-win.ll
@@ -0,0 +1,44 @@
+; RUN: llc < %s -mtriple=aarch64-windows -mattr=+neon | FileCheck %s
+
+; CHECK-LABEL: testmsxs:
+; CHECK: fcvtas w8, s0
+; CHECK-NEXT: sxtw x0, w8
+; CHECK-NEXT: ret
+define i64 @testmsxs(float %x) {
+entry:
+ %0 = tail call i32 @llvm.lround.i32.f32(float %x)
+ %conv = sext i32 %0 to i64
+ ret i64 %conv
+}
+
+; CHECK-LABEL: testmsws:
+; CHECK: fcvtas w0, s0
+; CHECK-NEXT: ret
+define i32 @testmsws(float %x) {
+entry:
+ %0 = tail call i32 @llvm.lround.i32.f32(float %x)
+ ret i32 %0
+}
+
+; CHECK-LABEL: testmsxd:
+; CHECK: fcvtas w8, d0
+; CHECK-NEXT: sxtw x0, w8
+; CHECK-NEXT: ret
+define i64 @testmsxd(double %x) {
+entry:
+ %0 = tail call i32 @llvm.lround.i32.f64(double %x)
+ %conv = sext i32 %0 to i64
+ ret i64 %conv
+}
+
+; CHECK-LABEL: testmswd:
+; CHECK: fcvtas w0, d0
+; CHECK-NEXT: ret
+define i32 @testmswd(double %x) {
+entry:
+ %0 = tail call i32 @llvm.lround.i32.f64(double %x)
+ ret i32 %0
+}
+
+declare i32 @llvm.lround.i32.f32(float) nounwind readnone
+declare i32 @llvm.lround.i32.f64(double) nounwind readnone
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