[llvm] r361192 - [AArch64] Handle lowering lround on windows, where long is 32 bit

[Martin Storsjo via llvm-commits]

Author: mstorsjo
Date: Mon May 20 12:53:28 2019
New Revision: 361192

URL: http://llvm.org/viewvc/llvm-project?rev=361192&view=rev
Log:
[AArch64] Handle lowering lround on windows, where long is 32 bit

Differential Revision: https://reviews.llvm.org/D62108

Added:
    llvm/trunk/test/CodeGen/AArch64/lround-conv-win.ll
Modified:
    llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td

Modified: llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td?rev=361192&r1=361191&r2=361192&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td Mon May 20 12:53:28 2019
@@ -3083,6 +3083,10 @@ defm : FPToIntegerPats<fp_to_uint, ftrun
 defm : FPToIntegerPats<fp_to_sint, fround, "FCVTAS">;
 defm : FPToIntegerPats<fp_to_uint, fround, "FCVTAU">;
 
+def : Pat<(i32 (lround f32:$Rn)),
+          (!cast<Instruction>(FCVTASUWSr) f32:$Rn)>;
+def : Pat<(i32 (lround f64:$Rn)),
+          (!cast<Instruction>(FCVTASUWDr) f64:$Rn)>;
 def : Pat<(i64 (lround f32:$Rn)),
           (!cast<Instruction>(FCVTASUXSr) f32:$Rn)>;
 def : Pat<(i64 (lround f64:$Rn)),

Added: llvm/trunk/test/CodeGen/AArch64/lround-conv-win.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/lround-conv-win.ll?rev=361192&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/lround-conv-win.ll (added)
+++ llvm/trunk/test/CodeGen/AArch64/lround-conv-win.ll Mon May 20 12:53:28 2019
@@ -0,0 +1,44 @@
+; RUN: llc < %s -mtriple=aarch64-windows -mattr=+neon | FileCheck %s
+
+; CHECK-LABEL: testmsxs:
+; CHECK:       fcvtas  w8, s0
+; CHECK-NEXT:  sxtw    x0, w8
+; CHECK-NEXT:  ret
+define i64 @testmsxs(float %x) {
+entry:
+  %0 = tail call i32 @llvm.lround.i32.f32(float %x)
+  %conv = sext i32 %0 to i64
+  ret i64 %conv
+}
+
+; CHECK-LABEL: testmsws:
+; CHECK:       fcvtas  w0, s0
+; CHECK-NEXT:  ret
+define i32 @testmsws(float %x) {
+entry:
+  %0 = tail call i32 @llvm.lround.i32.f32(float %x)
+  ret i32 %0
+}
+
+; CHECK-LABEL: testmsxd:
+; CHECK:       fcvtas  w8, d0
+; CHECK-NEXT:  sxtw    x0, w8
+; CHECK-NEXT:  ret
+define i64 @testmsxd(double %x) {
+entry:
+  %0 = tail call i32 @llvm.lround.i32.f64(double %x)
+  %conv = sext i32 %0 to i64
+  ret i64 %conv
+}
+
+; CHECK-LABEL: testmswd:
+; CHECK:       fcvtas  w0, d0
+; CHECK-NEXT:  ret
+define i32 @testmswd(double %x) {
+entry:
+  %0 = tail call i32 @llvm.lround.i32.f64(double %x)
+  ret i32 %0
+}
+
+declare i32 @llvm.lround.i32.f32(float) nounwind readnone
+declare i32 @llvm.lround.i32.f64(double) nounwind readnone