[llvm] r361167 - R600: Fix unconditional return in loop
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Mon May 20 09:22:11 PDT 2019
Author: arsenm
Date: Mon May 20 09:22:11 2019
New Revision: 361167
URL: http://llvm.org/viewvc/llvm-project?rev=361167&view=rev
Log:
R600: Fix unconditional return in loop
Modified:
llvm/trunk/lib/Target/AMDGPU/R600OptimizeVectorRegisters.cpp
Modified: llvm/trunk/lib/Target/AMDGPU/R600OptimizeVectorRegisters.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/R600OptimizeVectorRegisters.cpp?rev=361167&r1=361166&r2=361167&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/R600OptimizeVectorRegisters.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/R600OptimizeVectorRegisters.cpp Mon May 20 09:22:11 2019
@@ -56,17 +56,12 @@ using namespace llvm;
#define DEBUG_TYPE "vec-merger"
-static bool
-isImplicitlyDef(MachineRegisterInfo &MRI, unsigned Reg) {
- for (MachineRegisterInfo::def_instr_iterator It = MRI.def_instr_begin(Reg),
- E = MRI.def_instr_end(); It != E; ++It) {
- return (*It).isImplicitDef();
- }
- if (MRI.isReserved(Reg)) {
+static bool isImplicitlyDef(MachineRegisterInfo &MRI, unsigned Reg) {
+ assert(MRI.isSSA());
+ if (TargetRegisterInfo::isPhysicalRegister(Reg))
return false;
- }
- llvm_unreachable("Reg without a def");
- return false;
+ const MachineInstr *MI = MRI.getUniqueVRegDef(Reg);
+ return MI && MI->isImplicitDef();
}
namespace {
More information about the llvm-commits
mailing list