[PATCH] D62024: [InstCombine] fold shuffles of insert_subvectors

[Sanjay Patel via Phabricator via llvm-commits]

spatel added a comment.

In D62024#1507180 <https://reviews.llvm.org/D62024#1507180>, @efriedma wrote:

> In terms of describing it, what is the backend actually going to see?


Good question - I stepped through some examples, and I might've been overthinking this. We assume that the original shuffle was safe/legal because nothing in the IR optimizer should create anything difficult. So the initial DAG for these patterns appears to be the same independently of this IR transform:

  Before:
  define <4 x float> @widen_shuffles(<2 x float> %x, <2 x float> %y) {
    %s1 = shufflevector <2 x float> %x, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef> ; concat with undef elements
    %s2 = shufflevector <2 x float> %y, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef> ; concat with undef elements
    %s3 = shufflevector <4 x float> %s2, <4 x float> %s1, <4 x i32> <i32 1, i32 5, i32 4, i32 0> ; arbitrary shuffle
    ret <4 x float> %s3
  }
  
  $ llc -o - -debug
  ...
  Initial selection DAG: %bb.0 'widen_shuffles:'
          t9: v4f32 = concat_vectors t6, undef:v2f32
          t8: v4f32 = concat_vectors t3, undef:v2f32
        t10: v4f32 = vector_shuffle<1,5,4,0> t9, t8



  After:
  define <4 x float> @widen_shuffles(<2 x float> %x, <2 x float> %y) {
    %s3 = shufflevector <2 x float> %y, <2 x float> %x, <4 x i32> <i32 1, i32 3, i32 2, i32 0>
    ret <4 x float> %s3
  }
  
  $ llc -o - -debug
  ...
  Initial selection DAG: %bb.0 'widen_shuffles:'
          t8: v4f32 = concat_vectors t6, undef:v2f32
          t9: v4f32 = concat_vectors t3, undef:v2f32
        t10: v4f32 = vector_shuffle<1,5,4,0> t8, t9

So IIUC, this is always the 1st option that you listed: legal destination type with vector widening, so the backend shouldn't ever see a difference.


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