[PATCH] D62100: [DAGCombine][X86][AMDGPU][AArch64] (srl (shl x, c1), c2) with c1 != c2 handling

[Roman Lebedev via Phabricator via llvm-commits]

lebedev.ri added a comment.

Looks like AMDGPU changes are neutral too.
And now that i think about it, the AArch64 regression should be solvable (hidable) by an inverse transform.
Should i look into that before or after this patch?


Repository:
  rL LLVM

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  https://reviews.llvm.org/D62100/new/

https://reviews.llvm.org/D62100