[PATCH] D62100: [DAGCombine][X86][AMDGPU][AArch64] (srl (shl x, c1), c2) with c1 != c2 handling

[Roman Lebedev via Phabricator via llvm-commits]

lebedev.ri created this revision.
lebedev.ri added reviewers: RKSimon, craig.topper, spatel.
lebedev.ri added a project: LLVM.
Herald added subscribers: kristof.beyls, t-tye, tpr, dstuttard, javed.absar, yaxunl, nhaehnle, wdng, jvesely, kzhuravl.

https://rise4fun.com/Alive/6bVL

AArch64 is clearly a regression, will need a separate fix
AMDGPU change looks bad either way - `bfe` is not used
X86 changes look neutral-positive, except vector cases, those are clearly regressions


Repository:
  rL LLVM

https://reviews.llvm.org/D62100

Files:
  lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  test/CodeGen/AArch64/arm64-bitfield-extract.ll
  test/CodeGen/AMDGPU/llvm.amdgcn.ubfe.ll
  test/CodeGen/X86/pr32588.ll
  test/CodeGen/X86/pull-binop-through-shift.ll
  test/CodeGen/X86/rotate-extract-vector.ll
  test/CodeGen/X86/rotate-extract.ll
  test/CodeGen/X86/shift-mask.ll

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