[PATCH] D62058: [AMDGPU] gfx1010 Avoid SMEM WAR hazard for some s_waitcnt values

[Carl Ritson via Phabricator via llvm-commits]

critson marked an inline comment as done.
critson added inline comments.


================
Comment at: lib/Target/AMDGPU/GCNHazardRecognizer.cpp:927
       if (TII->isSALU(*MI)) {
+        // Reducing lgkmcnt count to 0 always mitigates the hazard.
+        if (MI->getOpcode() == AMDGPU::S_WAITCNT) {
+          const int64_t Imm = MI->getOperand(0).getImm();
+          AMDGPU::Waitcnt Decoded = AMDGPU::decodeWaitcnt(IV, Imm);
+          return (Decoded.LgkmCnt == 0);
+        } else if (MI->getOpcode() == AMDGPU::S_WAITCNT_LGKMCNT) {
+          if (MI->getOperand(0).getReg() != AMDGPU::SGPR_NULL) {
+            // lgkmcnt cannot be infered at compile time
+            return false;
+          }
+          return (MI->getOperand(1).getImm() == 0);
+        }
+
+        // No SOPP instructions can mitigate the hazard.
         if (TII->isSOPP(*MI))
           return false;
----------------
rampitec wrote:
> rampitec wrote:
> > I believe you still can immediately bail if it is no SOPP.
> Can you move that logic into the switch below?
S_WAITCNT is SOPP, so this test needs to be after evaluating S_WAITCNT.


Repository:
  rL LLVM

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D62058/new/

https://reviews.llvm.org/D62058