[llvm] r361040 - [AMDGPU][MC] Enabled labels with s_call_b64 and s_cbranch_i_fork
Dmitry Preobrazhensky via llvm-commits
llvm-commits at lists.llvm.org
Fri May 17 07:57:04 PDT 2019
Author: dpreobra
Date: Fri May 17 07:57:04 2019
New Revision: 361040
URL: http://llvm.org/viewvc/llvm-project?rev=361040&view=rev
Log:
[AMDGPU][MC] Enabled labels with s_call_b64 and s_cbranch_i_fork
See https://bugs.llvm.org/show_bug.cgi?id=41888
Reviewers: artem.tamazov, arsenm
Differential Revision: https://reviews.llvm.org/D62016
Added:
llvm/trunk/test/MC/AMDGPU/labels-branch-gfx9.s
Modified:
llvm/trunk/lib/Target/AMDGPU/SOPInstructions.td
llvm/trunk/test/MC/AMDGPU/sopk.s
llvm/trunk/test/MC/Disassembler/AMDGPU/sopk_gfx9.txt
llvm/trunk/test/MC/Disassembler/AMDGPU/sopk_vi.txt
Modified: llvm/trunk/lib/Target/AMDGPU/SOPInstructions.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SOPInstructions.td?rev=361040&r1=361039&r2=361040&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/SOPInstructions.td (original)
+++ llvm/trunk/lib/Target/AMDGPU/SOPInstructions.td Fri May 17 07:57:04 2019
@@ -720,7 +720,7 @@ let Defs = [SCC], isCommutable = 1, Disa
let SubtargetPredicate = isGFX6GFX7GFX8GFX9 in
def S_CBRANCH_I_FORK : SOPK_Pseudo <
"s_cbranch_i_fork",
- (outs), (ins SReg_64:$sdst, s16imm:$simm16),
+ (outs), (ins SReg_64:$sdst, sopp_brtarget:$simm16),
"$sdst, $simm16"
>;
@@ -771,7 +771,7 @@ let SubtargetPredicate = isGFX9Plus in {
def S_CALL_B64 : SOPK_Pseudo<
"s_call_b64",
(outs SReg_64:$sdst),
- (ins s16imm:$simm16),
+ (ins sopp_brtarget:$simm16),
"$sdst, $simm16"> {
let isCall = 1;
}
Added: llvm/trunk/test/MC/AMDGPU/labels-branch-gfx9.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AMDGPU/labels-branch-gfx9.s?rev=361040&view=auto
==============================================================================
--- llvm/trunk/test/MC/AMDGPU/labels-branch-gfx9.s (added)
+++ llvm/trunk/test/MC/AMDGPU/labels-branch-gfx9.s Fri May 17 07:57:04 2019
@@ -0,0 +1,19 @@
+// RUN: llvm-mc -arch=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck %s --check-prefix=GFX9
+// RUN: llvm-mc -arch=amdgcn -mcpu=gfx900 -filetype=obj %s | llvm-objdump -disassemble -mcpu=gfx900 - | FileCheck %s --check-prefix=BIN
+
+loop_start:
+
+s_call_b64 s[10:11], loop_end
+// GFX9: s_call_b64 s[10:11], loop_end ; encoding: [A,A,0x8a,0xba]
+// GFX9-NEXT: ; fixup A - offset: 0, value: loop_end, kind: fixup_si_sopp_br
+// BIN: loop_start:
+// BIN-NEXT: s_call_b64 s[10:11], loop_end // 000000000000: BA8A0001
+
+s_call_b64 s[10:11], loop_start
+// GFX9: s_call_b64 s[10:11], loop_start ; encoding: [A,A,0x8a,0xba]
+// GFX9-NEXT: ; fixup A - offset: 0, value: loop_start, kind: fixup_si_sopp_br
+// BIN: s_call_b64 s[10:11], loop_start // 000000000004: BA8AFFFE
+// BIN: loop_end:
+
+loop_end:
+ s_nop 0
Modified: llvm/trunk/test/MC/AMDGPU/sopk.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AMDGPU/sopk.s?rev=361040&r1=361039&r2=361040&view=diff
==============================================================================
--- llvm/trunk/test/MC/AMDGPU/sopk.s (original)
+++ llvm/trunk/test/MC/AMDGPU/sopk.s Fri May 17 07:57:04 2019
@@ -88,8 +88,8 @@ s_mulk_i32 s2, 0xFFFF
// VI9: s_mulk_i32 s2, 0xffff ; encoding: [0xff,0xff,0x82,0xb7]
s_cbranch_i_fork s[2:3], 0x6
-// SICI: s_cbranch_i_fork s[2:3], 0x6 ; encoding: [0x06,0x00,0x82,0xb8]
-// VI9: s_cbranch_i_fork s[2:3], 0x6 ; encoding: [0x06,0x00,0x02,0xb8]
+// SICI: s_cbranch_i_fork s[2:3], 6 ; encoding: [0x06,0x00,0x82,0xb8]
+// VI9: s_cbranch_i_fork s[2:3], 6 ; encoding: [0x06,0x00,0x02,0xb8]
// raw number mapped to known HW register
s_getreg_b32 s2, 0x6
@@ -282,13 +282,13 @@ s_endpgm_ordered_ps_done
// NOSICIVI: error: instruction not supported on this GPU
s_call_b64 s[12:13], 12609
-// GFX9: s_call_b64 s[12:13], 0x3141 ; encoding: [0x41,0x31,0x8c,0xba]
+// GFX9: s_call_b64 s[12:13], 12609 ; encoding: [0x41,0x31,0x8c,0xba]
// NOSICIVI: error: instruction not supported on this GPU
s_call_b64 s[100:101], 12609
-// GFX9: s_call_b64 s[100:101], 0x3141 ; encoding: [0x41,0x31,0xe4,0xba]
+// GFX9: s_call_b64 s[100:101], 12609 ; encoding: [0x41,0x31,0xe4,0xba]
// NOSICIVI: error: instruction not supported on this GPU
s_call_b64 s[10:11], 49617
-// GFX9: s_call_b64 s[10:11], 0xc1d1 ; encoding: [0xd1,0xc1,0x8a,0xba]
+// GFX9: s_call_b64 s[10:11], 49617 ; encoding: [0xd1,0xc1,0x8a,0xba]
// NOSICIVI: error: instruction not supported on this GPU
Modified: llvm/trunk/test/MC/Disassembler/AMDGPU/sopk_gfx9.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/AMDGPU/sopk_gfx9.txt?rev=361040&r1=361039&r2=361040&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/AMDGPU/sopk_gfx9.txt (original)
+++ llvm/trunk/test/MC/Disassembler/AMDGPU/sopk_gfx9.txt Fri May 17 07:57:04 2019
@@ -3,11 +3,11 @@
# GFX9: s_endpgm_ordered_ps_done ; encoding: [0x00,0x00,0x9e,0xbf]
0x00,0x00,0x9e,0xbf
-# GFX9: s_call_b64 s[10:11], 0x3141 ; encoding: [0x41,0x31,0x8a,0xba]
+# GFX9: s_call_b64 s[10:11], 12609 ; encoding: [0x41,0x31,0x8a,0xba]
0x41,0x31,0x8a,0xba
-# GFX9: s_call_b64 s[100:101], 0x3141 ; encoding: [0x41,0x31,0xe4,0xba]
+# GFX9: s_call_b64 s[100:101], 12609 ; encoding: [0x41,0x31,0xe4,0xba]
0x41,0x31,0xe4,0xba
-# GFX9: s_call_b64 s[10:11], 0xc1d1 ; encoding: [0xd1,0xc1,0x8a,0xba]
+# GFX9: s_call_b64 s[10:11], 49617 ; encoding: [0xd1,0xc1,0x8a,0xba]
0xd1,0xc1,0x8a,0xba
Modified: llvm/trunk/test/MC/Disassembler/AMDGPU/sopk_vi.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/AMDGPU/sopk_vi.txt?rev=361040&r1=361039&r2=361040&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/AMDGPU/sopk_vi.txt (original)
+++ llvm/trunk/test/MC/Disassembler/AMDGPU/sopk_vi.txt Fri May 17 07:57:04 2019
@@ -45,7 +45,7 @@
# VI: s_mulk_i32 s2, 0x6 ; encoding: [0x06,0x00,0x82,0xb7]
0x06 0x00 0x82 0xb7
-# VI: s_cbranch_i_fork s[2:3], 0x6 ; encoding: [0x06,0x00,0x02,0xb8]
+# VI: s_cbranch_i_fork s[2:3], 6 ; encoding: [0x06,0x00,0x02,0xb8]
0x06 0x00 0x02 0xb8
# VI: s_getreg_b32 s2, hwreg(HW_REG_LDS_ALLOC) ; encoding: [0x06,0xf8,0x82,0xb8]
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