[llvm] r361038 - [X86][AVX] Remove LowerCTTZ's AVX1 custom vector handling.

[Simon Pilgrim via llvm-commits]

Author: rksimon
Date: Fri May 17 07:37:19 2019
New Revision: 361038

URL: http://llvm.org/viewvc/llvm-project?rev=361038&view=rev
Log:
[X86][AVX] Remove LowerCTTZ's AVX1 custom vector handling.

We can now rely on generic expansion to handle this.

Modified:
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=361038&r1=361037&r2=361038&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Fri May 17 07:37:19 2019
@@ -1190,9 +1190,6 @@ X86TargetLowering::X86TargetLowering(con
       setOperationAction(ISD::CTPOP,           VT, Custom);
       setOperationAction(ISD::CTLZ,            VT, Custom);
 
-      // TODO - remove this once 256-bit X86ISD::ANDNP correctly split.
-      setOperationAction(ISD::CTTZ,  VT, HasInt256 ? Expand : Custom);
-
       // The condition codes aren't legal in SSE/AVX and under AVX512 we use
       // setcc all the way to isel and prefer SETGT in some isel patterns.
       setCondCodeAction(ISD::SETLT, VT, Custom);
@@ -24018,10 +24015,6 @@ static SDValue LowerCTTZ(SDValue Op, con
   SDValue N0 = Op.getOperand(0);
   SDLoc dl(Op);
 
-  // Decompose 256-bit ops into smaller 128-bit ops.
-  if (VT.is256BitVector() && !Subtarget.hasInt256())
-    return Lower256IntUnary(Op, DAG);
-
   assert(!VT.isVector() && Op.getOpcode() == ISD::CTTZ &&
          "Only scalar CTTZ requires custom lowering");