[PATCH] D61773: [RISCV] Add CFI directives for RISCV prologue/epilog.

[Hsiangkai Wang via Phabricator via llvm-commits]

HsiangKai updated this revision to Diff 199958.
HsiangKai added a comment.

Update test cases.


Repository:
  rL LLVM

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D61773/new/

https://reviews.llvm.org/D61773

Files:
  lib/Target/RISCV/MCTargetDesc/RISCVMCAsmInfo.cpp
  lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp
  lib/Target/RISCV/RISCVFrameLowering.cpp
  test/CodeGen/RISCV/addc-adde-sube-subc.ll
  test/CodeGen/RISCV/alu64.ll
  test/CodeGen/RISCV/atomic-cmpxchg-flag.ll
  test/CodeGen/RISCV/bare-select.ll
  test/CodeGen/RISCV/branch-relaxation.ll
  test/CodeGen/RISCV/branch.ll
  test/CodeGen/RISCV/frame-info.ll
  test/CodeGen/RISCV/get-setcc-result-type.ll
  test/CodeGen/RISCV/hoist-global-addr-base.ll
  test/CodeGen/RISCV/inline-asm.ll
  test/CodeGen/RISCV/jumptable.ll
  test/CodeGen/RISCV/legalize-fneg.ll
  test/CodeGen/RISCV/rotl-rotr.ll
  test/CodeGen/RISCV/rv64i-tricky-shifts.ll
  test/CodeGen/RISCV/select-cc.ll
  test/CodeGen/RISCV/sext-zext-trunc.ll
  test/CodeGen/RISCV/tail-calls.ll
  test/CodeGen/RISCV/zext-with-load-is-free.ll

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