[PATCH] D62017: [CodeGen] Add lrint/llrint builtins

[Adhemerval Zanella via Phabricator via llvm-commits]

zatrazz created this revision.
zatrazz added reviewers: efriedma, rengolin, javed.absar, huntergr, SjoerdMeijer, t.p.northover, echristo, evandro, craig.topper.
zatrazz added a project: LLVM.
Herald added subscribers: jsji, atanasyan, jrtc27, hiraditya, kristof.beyls, nemanjai, sdardis.

This patch add the ISD::LRINT and ISD::LLRINT along with new
intrinsics.  The changes are straightforward as for other
floating-point rounding functions, with just some adjustments
required to handle the return value being an integer.

The idea is to optimize lrint/llrint generation for AArch64
in a subsequent patch.  Current semantic is just route it to libm
symbol.

(This is patch is similar to D61390 <https://reviews.llvm.org/D61390>).


Repository:
  rL LLVM

https://reviews.llvm.org/D62017

Files:
  llvm/docs/LangRef.rst
  llvm/include/llvm/CodeGen/ISDOpcodes.h
  llvm/include/llvm/IR/Intrinsics.td
  llvm/include/llvm/IR/RuntimeLibcalls.def
  llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
  llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
  llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
  llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
  llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
  llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp
  llvm/lib/CodeGen/TargetLoweringBase.cpp
  llvm/lib/Target/X86/X86ISelLowering.cpp
  llvm/test/CodeGen/AArch64/llrint-conv.ll
  llvm/test/CodeGen/AArch64/lrint-conv.ll
  llvm/test/CodeGen/ARM/llrint-conv.ll
  llvm/test/CodeGen/ARM/lrint-conv.ll
  llvm/test/CodeGen/Mips/llrint-conv.ll
  llvm/test/CodeGen/Mips/lrint-conv.ll
  llvm/test/CodeGen/PowerPC/llrint-conv.ll
  llvm/test/CodeGen/PowerPC/lrint-conv.ll
  llvm/test/CodeGen/X86/llrint-conv-i32.ll
  llvm/test/CodeGen/X86/llrint-conv.ll
  llvm/test/CodeGen/X86/lrint-conv-i32.ll
  llvm/test/CodeGen/X86/lrint-conv.ll

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