[llvm] r360894 - [AArch64] Handle ISD::LROUND and ISD::LLROUND
Adhemerval Zanella via llvm-commits
llvm-commits at lists.llvm.org
Thu May 16 06:30:18 PDT 2019
Author: azanella
Date: Thu May 16 06:30:18 2019
New Revision: 360894
URL: http://llvm.org/viewvc/llvm-project?rev=360894&view=rev
Log:
[AArch64] Handle ISD::LROUND and ISD::LLROUND
This patch optimizes ISD::LROUND and ISD::LLROUND to fcvtas
instruction. It currently only handles the scalar version.
Modified:
llvm/trunk/include/llvm/Target/TargetSelectionDAG.td
llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp
llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td
llvm/trunk/test/CodeGen/AArch64/llround-conv.ll
llvm/trunk/test/CodeGen/AArch64/lround-conv.ll
Modified: llvm/trunk/include/llvm/Target/TargetSelectionDAG.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetSelectionDAG.td?rev=360894&r1=360893&r2=360894&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Target/TargetSelectionDAG.td (original)
+++ llvm/trunk/include/llvm/Target/TargetSelectionDAG.td Thu May 16 06:30:18 2019
@@ -450,6 +450,9 @@ def ffloor : SDNode<"ISD::FFLOOR"
def fnearbyint : SDNode<"ISD::FNEARBYINT" , SDTFPUnaryOp>;
def fround : SDNode<"ISD::FROUND" , SDTFPUnaryOp>;
+def lround : SDNode<"ISD::LROUND" , SDTFPToIntOp>;
+def llround : SDNode<"ISD::LLROUND" , SDTFPToIntOp>;
+
def fpround : SDNode<"ISD::FP_ROUND" , SDTFPRoundOp>;
def fpextend : SDNode<"ISD::FP_EXTEND" , SDTFPExtendOp>;
def fcopysign : SDNode<"ISD::FCOPYSIGN" , SDTFPSignOp>;
Modified: llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp?rev=360894&r1=360893&r2=360894&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp Thu May 16 06:30:18 2019
@@ -457,6 +457,8 @@ AArch64TargetLowering::AArch64TargetLowe
setOperationAction(ISD::FMAXNUM, Ty, Legal);
setOperationAction(ISD::FMINIMUM, Ty, Legal);
setOperationAction(ISD::FMAXIMUM, Ty, Legal);
+ setOperationAction(ISD::LROUND, Ty, Legal);
+ setOperationAction(ISD::LLROUND, Ty, Legal);
}
if (Subtarget->hasFullFP16()) {
Modified: llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td?rev=360894&r1=360893&r2=360894&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td Thu May 16 06:30:18 2019
@@ -3083,6 +3083,15 @@ defm : FPToIntegerPats<fp_to_uint, ftrun
defm : FPToIntegerPats<fp_to_sint, fround, "FCVTAS">;
defm : FPToIntegerPats<fp_to_uint, fround, "FCVTAU">;
+def : Pat<(i64 (lround f32:$Rn)),
+ (!cast<Instruction>(FCVTASUXSr) f32:$Rn)>;
+def : Pat<(i64 (lround f64:$Rn)),
+ (!cast<Instruction>(FCVTASUXDr) f64:$Rn)>;
+def : Pat<(i64 (llround f32:$Rn)),
+ (!cast<Instruction>(FCVTASUXSr) f32:$Rn)>;
+def : Pat<(i64 (llround f64:$Rn)),
+ (!cast<Instruction>(FCVTASUXDr) f64:$Rn)>;
+
//===----------------------------------------------------------------------===//
// Scaled integer to floating point conversion instructions.
//===----------------------------------------------------------------------===//
Modified: llvm/trunk/test/CodeGen/AArch64/llround-conv.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/llround-conv.ll?rev=360894&r1=360893&r2=360894&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/llround-conv.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/llround-conv.ll Thu May 16 06:30:18 2019
@@ -1,7 +1,8 @@
; RUN: llc < %s -mtriple=aarch64 -mattr=+neon | FileCheck %s
; CHECK-LABEL: testmsws:
-; CHECK: bl llroundf
+; CHECK: fcvtas x0, s0
+; CHECK: ret
define i32 @testmsws(float %x) {
entry:
%0 = tail call i64 @llvm.llround.f32(float %x)
@@ -10,7 +11,8 @@ entry:
}
; CHECK-LABEL: testmsxs:
-; CHECK: b llroundf
+; CHECK: fcvtas x0, s0
+; CHECK-NEXT: ret
define i64 @testmsxs(float %x) {
entry:
%0 = tail call i64 @llvm.llround.f32(float %x)
@@ -18,7 +20,8 @@ entry:
}
; CHECK-LABEL: testmswd:
-; CHECK: bl llround
+; CHECK: fcvtas x0, d0
+; CHECK: ret
define i32 @testmswd(double %x) {
entry:
%0 = tail call i64 @llvm.llround.f64(double %x)
@@ -27,7 +30,8 @@ entry:
}
; CHECK-LABEL: testmsxd:
-; CHECK: b llround
+; CHECK: fcvtas x0, d0
+; CHECK-NEXT: ret
define i64 @testmsxd(double %x) {
entry:
%0 = tail call i64 @llvm.llround.f64(double %x)
Modified: llvm/trunk/test/CodeGen/AArch64/lround-conv.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/lround-conv.ll?rev=360894&r1=360893&r2=360894&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/lround-conv.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/lround-conv.ll Thu May 16 06:30:18 2019
@@ -1,7 +1,8 @@
; RUN: llc < %s -mtriple=aarch64 -mattr=+neon | FileCheck %s
; CHECK-LABEL: testmsws:
-; CHECK: bl lroundf
+; CHECK: fcvtas x0, s0
+; CHECK: ret
define i32 @testmsws(float %x) {
entry:
%0 = tail call i64 @llvm.lround.i64.f32(float %x)
@@ -10,7 +11,8 @@ entry:
}
; CHECK-LABEL: testmsxs:
-; CHECK: b lroundf
+; CHECK: fcvtas x0, s0
+; CHECK-NEXT: ret
define i64 @testmsxs(float %x) {
entry:
%0 = tail call i64 @llvm.lround.i64.f32(float %x)
@@ -18,7 +20,8 @@ entry:
}
; CHECK-LABEL: testmswd:
-; CHECK: bl lround
+; CHECK: fcvtas x0, d0
+; CHECK: ret
define i32 @testmswd(double %x) {
entry:
%0 = tail call i64 @llvm.lround.i64.f64(double %x)
@@ -27,7 +30,8 @@ entry:
}
; CHECK-LABEL: testmsxd:
-; CHECK: b lround
+; CHECK: fcvtas x0, d0
+; CHECK-NEXT: ret
define i64 @testmsxd(double %x) {
entry:
%0 = tail call i64 @llvm.lround.i64.f64(double %x)
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