[PATCH] D60365: [AVR] Fix codegen for rotate instructions

[Dylan McKay via Phabricator via llvm-commits]

dylanmckay added inline comments.


================
Comment at: llvm/lib/Target/AVR/AVRExpandPseudoInsts.cpp:1273
+  // Put 0 in zero register
+  ZeroReg = scavengeGPR8(MI);
+  buildMI(MBB, MBBI, OpLoad)
----------------
This variable is called `ZeroReg`, and reading the code my inference is that the `ZeroReg` contains the register number of the zero-register, `r1`, which is a register that, [according to the calling convention](https://gcc.gnu.org/wiki/avr-gcc), is always guaranteed to contain the value `0`.

I recommend either modifying the logic to use the dedicated zero register instead of a scavenged temporary, or renaming the variable from `ZeroReg` to something like `TempRegWithZero`.


================
Comment at: llvm/lib/Target/AVR/AVRExpandPseudoInsts.cpp:1319
+
+  // Put 0 in temporary register
+  TmpReg = scavengeGPR8(MI);
----------------
Same here re. dedicated zero register.


Repository:
  rL LLVM

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D60365/new/

https://reviews.llvm.org/D60365