[PATCH] D61973: [AArch64] Support .reloc *, R_AARCH64_NONE, *
Fangrui Song via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed May 15 18:48:24 PDT 2019
MaskRay created this revision.
MaskRay added reviewers: peter.smith, rprichard.
Herald added subscribers: llvm-commits, atanasyan, kristof.beyls, arichardson, javed.absar, sdardis.
Herald added a project: LLVM.
This can be used to create references among sections. When --gc-sections
is used, the referenced section will be retained if the origin section
is retained.
fixup_aarch64_NONE is similar to fixup_Mips_NONE.
Repository:
rL LLVM
https://reviews.llvm.org/D61973
Files:
lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp
lib/Target/AArch64/MCTargetDesc/AArch64ELFObjectWriter.cpp
lib/Target/AArch64/MCTargetDesc/AArch64FixupKinds.h
Index: lib/Target/AArch64/MCTargetDesc/AArch64FixupKinds.h
===================================================================
--- lib/Target/AArch64/MCTargetDesc/AArch64FixupKinds.h
+++ lib/Target/AArch64/MCTargetDesc/AArch64FixupKinds.h
@@ -15,8 +15,11 @@
namespace AArch64 {
enum Fixups {
+ // Fixups resulting in R_AARCH64_NONE.
+ fixup_aarch64_NONE = FirstTargetFixupKind,
+
// A 21-bit pc-relative immediate inserted into an ADR instruction.
- fixup_aarch64_pcrel_adr_imm21 = FirstTargetFixupKind,
+ fixup_aarch64_pcrel_adr_imm21,
// A 21-bit pc-relative immediate inserted into an ADRP instruction.
fixup_aarch64_pcrel_adrp_imm21,
Index: lib/Target/AArch64/MCTargetDesc/AArch64ELFObjectWriter.cpp
===================================================================
--- lib/Target/AArch64/MCTargetDesc/AArch64ELFObjectWriter.cpp
+++ lib/Target/AArch64/MCTargetDesc/AArch64ELFObjectWriter.cpp
@@ -200,6 +200,8 @@
return ELF::R_AARCH64_NONE;
} else
return ELF::R_AARCH64_ABS64;
+ case AArch64::fixup_aarch64_NONE:
+ return ELF::R_AARCH64_NONE;
case AArch64::fixup_aarch64_add_imm12:
if (RefKind == AArch64MCExpr::VK_DTPREL_HI12)
return R_CLS(TLSLD_ADD_DTPREL_HI12);
Index: lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp
===================================================================
--- lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp
+++ lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp
@@ -41,12 +41,15 @@
return AArch64::NumTargetFixupKinds;
}
+ Optional<MCFixupKind> getFixupKind(StringRef Name) const override;
+
const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override {
const static MCFixupKindInfo Infos[AArch64::NumTargetFixupKinds] = {
// This table *must* be in the order that the fixup_* kinds are defined
// in AArch64FixupKinds.h.
//
// Name Offset (bits) Size (bits) Flags
+ {"fixup_aarch64_NONE", 0, 0, 0},
{"fixup_aarch64_pcrel_adr_imm21", 0, 32, PCRelFlagVal},
{"fixup_aarch64_pcrel_adrp_imm21", 0, 32, PCRelFlagVal},
{"fixup_aarch64_add_imm12", 10, 12, 0},
@@ -103,6 +106,7 @@
default:
llvm_unreachable("Unknown fixup kind!");
+ case AArch64::fixup_aarch64_NONE:
case AArch64::fixup_aarch64_tlsdesc_call:
return 0;
@@ -304,6 +308,7 @@
if (Value & 0x3)
Ctx.reportError(Fixup.getLoc(), "fixup not sufficiently aligned");
return (Value >> 2) & 0x3ffffff;
+ case AArch64::fixup_aarch64_NONE:
case FK_Data_1:
case FK_Data_2:
case FK_Data_4:
@@ -314,6 +319,12 @@
}
}
+Optional<MCFixupKind> AArch64AsmBackend::getFixupKind(StringRef Name) const {
+ if (Name == "R_AARCH64_NONE")
+ return (MCFixupKind)AArch64::fixup_aarch64_NONE;
+ return MCAsmBackend::getFixupKind(Name);
+}
+
/// getFixupKindContainereSizeInBytes - The number of bytes of the
/// container involved in big endian or 0 if the item is little endian
unsigned AArch64AsmBackend::getFixupKindContainereSizeInBytes(unsigned Kind) const {
-------------- next part --------------
A non-text attachment was scrubbed...
Name: D61973.199713.patch
Type: text/x-patch
Size: 3110 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20190516/5345e5d3/attachment.bin>
More information about the llvm-commits
mailing list