[PATCH] D59990: AMDGPU. Divergence driven ISel. Assign register class for cross block values according to the divergence.

[Stanislav Mekhanoshin via Phabricator via llvm-commits]

rampitec added inline comments.


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Comment at: include/llvm/CodeGen/FunctionLoweringInfo.h:246
+
+  unsigned CreateRegs(const Value * V);
 
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Formatting.


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Comment at: include/llvm/CodeGen/FunctionLoweringInfo.h:248
 
-  unsigned CreateRegs(Type *Ty);
+  unsigned CreateRegs(Type * Ty, bool isDivergent = false);
 
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Formatting.


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Comment at: lib/CodeGen/SelectionDAG/InstrEmitter.cpp:294
       const TargetRegisterClass *RC =
-        TLI->getRegClassFor(Op.getSimpleValueType());
+        TLI->getRegClassFor(Op.getSimpleValueType(),
+         Op.getNode()->isDivergent());
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Formatting.


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Comment at: lib/CodeGen/SelectionDAG/InstrEmitter.cpp:593
+    const TargetRegisterClass *SRC = TLI->getRegClassFor(Node->getSimpleValueType(0),
+    Node->isDivergent());
     SRC = TRI->getSubClassWithSubReg(SRC, SubIdx);
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Formatting.


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Comment at: lib/Target/AMDGPU/SIFixSGPRCopies.cpp:635
+                unsigned Reg = UseMI->getOperand(0).getReg();
+                if (TRI->isPhysicalRegister(Reg)) {
+                  if (!TRI->isSGPRReg(MRI, Reg)) {
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rampitec wrote:
> I think you can decrease nesting here. At the very least join individual "if" conditions with "&&".
You can still decrease nesting.


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Comment at: lib/Target/AMDGPU/SIISelLowering.cpp:9638
     MVT VT = Src0.getValueType().getSimpleVT();
-    const TargetRegisterClass *RC = getRegClassFor(VT);
+    const TargetRegisterClass *RC = getRegClassFor(VT,
+     Src0.getNode()->isDivergent());
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Formatting.


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Comment at: lib/Target/AMDGPU/SIISelLowering.h:370
   AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *) const override;
-
+  virtual const TargetRegisterClass *getRegClassFor(MVT VT,
+   bool isDivergent) const override;
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Formatting.


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Comment at: lib/Target/ARM/ARMISelLowering.cpp:1432
 /// specified value type.
-const TargetRegisterClass *ARMTargetLowering::getRegClassFor(MVT VT) const {
+const TargetRegisterClass *ARMTargetLowering::getRegClassFor(MVT VT,
+  bool isDivergent) const {
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Formatting.


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Comment at: lib/Target/ARM/ARMISelLowering.h:459
     /// specified value type.
-    const TargetRegisterClass *getRegClassFor(MVT VT) const override;
+    const TargetRegisterClass *getRegClassFor(MVT VT,
+      bool isDivergent=false) const override;
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Formatting.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D59990/new/

https://reviews.llvm.org/D59990