[PATCH] D61812: [AMDGPU] Fixed handling of imemdiate i1 literals

[Stanislav Mekhanoshin via Phabricator via llvm-commits]

rampitec marked 2 inline comments as done.
rampitec added inline comments.


================
Comment at: test/CodeGen/AMDGPU/xor3-i1-const.ll:9-19
+  %tmp26 = fcmp nsz olt float %arg1, 0.000000e+00
+  %tmp28 = call nsz float @llvm.amdgcn.interp.p2(float undef, float undef, i32 0, i32 0, i32 %arg2)
+  %tmp29 = fcmp nsz olt float %arg1, 5.700000e+01
+  %tmp31 = fcmp nsz olt float %tmp28, 0.000000e+00
+  %.demorgan = and i1 %tmp26, %tmp29
+  %tmp34 = xor i1 %.demorgan, true
+  %tmp35 = and i1 %tmp31, %tmp34
----------------
arsenm wrote:
> This could probably be reduced a bit
I was unable to reduce it further. Combine conditions are peculiar.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D61812/new/

https://reviews.llvm.org/D61812