[PATCH] D61862: Use an offset from TOS for idempotent rmw locked op lowering

[JF Bastien via Phabricator via llvm-commits]

jfb accepted this revision.
jfb added a subscriber: chandlerc.
jfb added a comment.
This revision is now accepted and ready to land.

One question for Chandler (which can be addressed as a follow up), otherwise LGTM.



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Comment at: test/CodeGen/X86/speculative-load-hardening.ll:1148
 ; hardcoded reference to RSP+offset.
 define void @idempotent_atomic(i32* %x) speculative_load_hardening {
 ; X64-LABEL: idempotent_atomic:
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I only just thought about this: should we stick to `mfence` when the function has attribute `speculative_load_hardening`? `mfence` forces much stronger ordering, and doesn't perform an idempotent load / store from the stack (which in this case brings in a new cacheline). Maybe @chandlerc should chime in.


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https://reviews.llvm.org/D61862