[llvm] r360686 - [AMDGPU] gfx1010 Strengthen some SMEM WAR hazard unit tests. NFC.

[Stanislav Mekhanoshin via llvm-commits]

Author: rampitec
Date: Tue May 14 09:04:03 2019
New Revision: 360686

URL: http://llvm.org/viewvc/llvm-project?rev=360686&view=rev
Log:
[AMDGPU] gfx1010 Strengthen some SMEM WAR hazard unit tests. NFC.

Tighten conditions on SMEM WAR hazard unit tests to ensure rejection
of workaround insertion where a s_waitcnt is present in dependency
chain. The current workaround code already conforms to these revise
tests.

Modified:
    llvm/trunk/test/CodeGen/AMDGPU/smem-war-hazard.mir

Modified: llvm/trunk/test/CodeGen/AMDGPU/smem-war-hazard.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/smem-war-hazard.mir?rev=360686&r1=360685&r2=360686&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/smem-war-hazard.mir (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/smem-war-hazard.mir Tue May 14 09:04:03 2019
@@ -31,8 +31,8 @@ body: |
 
 # GCN-LABEL: name: hazard_smem_war_related_clause
 # GCN:      S_LOAD_DWORD_IMM
-# GCN:      S_WAITCNT
-# GCN:      S_ADD_U32
+# GCN-NEXT: S_WAITCNT
+# GCN-NEXT: S_ADD_U32
 # GCN-NEXT: V_CMP_EQ_F32
 ---
 name: hazard_smem_war_related_clause
@@ -44,6 +44,23 @@ body: |
     $sgpr3 = S_ADD_U32 $sgpr2, $sgpr4, implicit-def $scc
     $sgpr0_sgpr1 = V_CMP_EQ_F32_e64 0, $vgpr0, 0, $vgpr1, 1, implicit $exec
     S_ENDPGM 0
+...
+
+# GCN-LABEL: name: hazard_smem_war_related_clause_vmcnt
+# GCN:      S_LOAD_DWORD_IMM
+# GCN-NEXT: S_WAITCNT 3952{{$}}
+# GCN-NEXT: S_ADD_U32
+# GCN-NEXT: V_CMP_EQ_F32
+---
+name: hazard_smem_war_related_clause_vmcnt
+body: |
+  bb.0:
+    liveins: $sgpr0, $sgpr1, $sgpr4, $vgpr0, $vgpr1
+    $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0, 0
+    S_WAITCNT 3952
+    $sgpr3 = S_ADD_U32 $sgpr2, $sgpr4, implicit-def $scc
+    $sgpr0_sgpr1 = V_CMP_EQ_F32_e64 0, $vgpr0, 0, $vgpr1, 1, implicit $exec
+    S_ENDPGM 0
 ...
 
 # GCN-LABEL: name: hazard_smem_war_branch