[PATCH] D61873: [PowerPC] P9 Scheduling Model: dispatching rule fixes

[Jinsong Ji via Phabricator via llvm-commits]

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This is to address some of the problems in existing P9 <https://reviews.llvm.org/P9> resource modeling,
especially about the dispatching rules.

Instead of using a hypothetical DISPATCHER , we try to use the number of actual dispatch slots,
and define SchedWriteRes to model dispatch rules, 
then update instruction classes according to dispatch rules.

All the dispatch rules and instruction classes update are made according
to POWER9 User Manual.

SPEC2017 benchmark test on P9 <https://reviews.llvm.org/P9> machines shows some improvement in 525.x264_r and 502.gcc_r, 
no big degradation for others.


Repository:
  rL LLVM

https://reviews.llvm.org/D61873

Files:
  llvm/lib/Target/PowerPC/P9InstrResources.td
  llvm/lib/Target/PowerPC/PPCScheduleP9.td
  llvm/test/CodeGen/PowerPC/build-vector-tests.ll
  llvm/test/CodeGen/PowerPC/vec_conv_fp32_to_i8_elts.ll

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