[PATCH] D61863: Prefer locked stack op over mfence for seq_cst stores

[Philip Reames via Phabricator via llvm-commits]

reames created this revision.
reames added reviewers: jfb, craig.topper.
Herald added subscribers: dexonsmith, bollu, mcrosier.
Herald added a project: LLVM.

This is a follow on to D58632 <https://reviews.llvm.org/D58632>, with the same logic.  Given a memory operation which needs ordering, but doesn't need to modify any particular address, prefer to use a locked stack op over an mfence.


Repository:
  rL LLVM

https://reviews.llvm.org/D61863

Files:
  lib/Target/X86/X86ISelLowering.cpp
  test/CodeGen/X86/atomic-load-store-wide.ll
  test/CodeGen/X86/atomic-non-integer.ll


Index: test/CodeGen/X86/atomic-non-integer.ll
===================================================================
--- test/CodeGen/X86/atomic-non-integer.ll
+++ test/CodeGen/X86/atomic-non-integer.ll
@@ -710,7 +710,7 @@
 ; X86-SSE2-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; X86-SSE2-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
 ; X86-SSE2-NEXT:    movlps %xmm0, (%eax)
-; X86-SSE2-NEXT:    mfence
+; X86-SSE2-NEXT:    lock orl $0, (%esp)
 ; X86-SSE2-NEXT:    retl
 ;
 ; X86-AVX-LABEL: store_double_seq_cst:
@@ -718,7 +718,7 @@
 ; X86-AVX-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; X86-AVX-NEXT:    vmovsd {{.*#+}} xmm0 = mem[0],zero
 ; X86-AVX-NEXT:    vmovlps %xmm0, (%eax)
-; X86-AVX-NEXT:    mfence
+; X86-AVX-NEXT:    lock orl $0, (%esp)
 ; X86-AVX-NEXT:    retl
 ;
 ; X86-NOSSE-LABEL: store_double_seq_cst:
Index: test/CodeGen/X86/atomic-load-store-wide.ll
===================================================================
--- test/CodeGen/X86/atomic-load-store-wide.ll
+++ test/CodeGen/X86/atomic-load-store-wide.ll
@@ -11,7 +11,7 @@
 ; SSE42-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; SSE42-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
 ; SSE42-NEXT:    movlps %xmm0, (%eax)
-; SSE42-NEXT:    mfence
+; SSE42-NEXT:    lock orl $0, (%esp)
 ; SSE42-NEXT:    retl
 ;
 ; NOSSE-LABEL: test1:
Index: lib/Target/X86/X86ISelLowering.cpp
===================================================================
--- lib/Target/X86/X86ISelLowering.cpp
+++ lib/Target/X86/X86ISelLowering.cpp
@@ -26425,7 +26425,7 @@
 
       // If this is a sequentially consistent store, also emit an mfence.
       if (IsSeqCst)
-        Chain = DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Chain);
+        Chain = emitLockedStackOp(DAG, Subtarget, Chain, dl);
 
       return Chain;
     }


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