[PATCH] D61821: gn build: add RISCV target
Nico Weber via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Mon May 13 09:56:22 PDT 2019
thakis added a comment.
Awesome, thanks! Just one real question, the last comment below:
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Comment at: llvm/utils/gn/secondary/llvm/lib/Target/RISCV/BUILD.gn:30
+ ":LLVMRISCVCodeGen",
+ "Utils",
+ ]
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I think this is the first target that has Utils depending on the higher-up tablegen target. What is this needed for?
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Comment at: llvm/utils/gn/secondary/llvm/lib/Target/RISCV/MCTargetDesc/BUILD.gn:4
+tablegen("RISCVGenAsmWriter") {
+ visibility = [ ":tablegen" ]
+ args = [ "-gen-asm-writer" ]
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Can you do https://reviews.llvm.org/D61859 for this file?
================
Comment at: llvm/utils/gn/secondary/llvm/lib/Target/RISCV/Utils/BUILD.gn:11
+ "//llvm/lib/Support",
+ "//llvm/lib/Target/RISCV/MCTargetDesc:tablegen",
+ ]
----------------
That's a bit unfortunate :/ I think ARM has this too, but it's a bit yucky. It'd be nicer if BaseInfo wouldn't depend on MCTargetDesc's tablegen internals.
================
Comment at: llvm/utils/gn/secondary/llvm/lib/Target/targets.gni:26
"Hexagon",
"Lanai",
----------------
(pass `-U9999` to git diff when generating diffs, so that phab doesn't have to say "Context not available.")
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Comment at: llvm/utils/gn/secondary/llvm/lib/Target/targets.gni:44
llvm_build_PowerPC = false
+llvm_build_RISCV = false
llvm_build_Sparc = false
----------------
Since nothing currently reads this, consider not having this variable (and giving the else below an empty body). But up to you, doesn't matter much.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D61821/new/
https://reviews.llvm.org/D61821
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