[PATCH] D61812: [AMDGPU] Fixed handling of imemdiate i1 literals

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


================
Comment at: lib/Target/AMDGPU/SIInstrInfo.cpp:2526
   switch (Imm.getBitWidth()) {
+  case 1: // This likely will be a condition code mask.
+    return false;
----------------
I don’t understand where this is coming from. There should be no 1-bit immediates anywhere?


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D61812/new/

https://reviews.llvm.org/D61812