[llvm] r360534 - [DAG] Add SimplifyDemandedBits support for BITREVERSE

[Simon Pilgrim via llvm-commits]

Author: rksimon
Date: Sat May 11 13:56:05 2019
New Revision: 360534

URL: http://llvm.org/viewvc/llvm-project?rev=360534&view=rev
Log:
[DAG] Add SimplifyDemandedBits support for BITREVERSE

Pulled out of D58017 while I continue to investigate the BSWAP regression on PPC

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp
    llvm/trunk/test/CodeGen/AMDGPU/bitreverse.ll
    llvm/trunk/test/CodeGen/X86/combine-bitreverse.ll

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp?rev=360534&r1=360533&r2=360534&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp Sat May 11 13:56:05 2019
@@ -1268,6 +1268,16 @@ bool TargetLowering::SimplifyDemandedBit
     }
     break;
   }
+  case ISD::BITREVERSE: {
+    SDValue Src = Op.getOperand(0);
+    APInt DemandedSrcBits = DemandedBits.reverseBits();
+    if (SimplifyDemandedBits(Src, DemandedSrcBits, DemandedElts, Known2, TLO,
+                             Depth + 1))
+      return true;
+    Known.One = Known2.One.reverseBits();
+    Known.Zero = Known2.Zero.reverseBits();
+    break;
+  }
   case ISD::SIGN_EXTEND_INREG: {
     SDValue Op0 = Op.getOperand(0);
     EVT ExVT = cast<VTSDNode>(Op.getOperand(1))->getVT();

Modified: llvm/trunk/test/CodeGen/AMDGPU/bitreverse.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/bitreverse.ll?rev=360534&r1=360533&r2=360534&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/bitreverse.ll (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/bitreverse.ll Sat May 11 13:56:05 2019
@@ -36,7 +36,6 @@ define amdgpu_kernel void @s_brev_i16(i1
 ; FLAT-NEXT:    s_mov_b32 s7, 0xf000
 ; FLAT-NEXT:    s_mov_b32 s6, -1
 ; FLAT-NEXT:    s_waitcnt lgkmcnt(0)
-; FLAT-NEXT:    s_and_b32 s0, s0, 0xffff
 ; FLAT-NEXT:    s_brev_b32 s0, s0
 ; FLAT-NEXT:    s_lshr_b32 s0, s0, 16
 ; FLAT-NEXT:    v_mov_b32_e32 v0, s0
@@ -1020,7 +1019,7 @@ define float @missing_truncate_promote_b
 ; FLAT-LABEL: missing_truncate_promote_bitreverse:
 ; FLAT:       ; %bb.0: ; %bb
 ; FLAT-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; FLAT-NEXT:    v_bfrev_b32_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+; FLAT-NEXT:    v_bfrev_b32_e32 v0, v0
 ; FLAT-NEXT:    v_cvt_f32_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
 ; FLAT-NEXT:    s_setpc_b64 s[30:31]
 bb:

Modified: llvm/trunk/test/CodeGen/X86/combine-bitreverse.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/combine-bitreverse.ll?rev=360534&r1=360533&r2=360534&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/combine-bitreverse.ll (original)
+++ llvm/trunk/test/CodeGen/X86/combine-bitreverse.ll Sat May 11 13:56:05 2019
@@ -40,7 +40,6 @@ define i32 @test_bitreverse_bitreverse(i
 define <4 x i32> @test_demandedbits_bitreverse(<4 x i32> %a0) nounwind {
 ; X86-LABEL: test_demandedbits_bitreverse:
 ; X86:       # %bb.0:
-; X86-NEXT:    por {{\.LCPI.*}}, %xmm0
 ; X86-NEXT:    pxor %xmm1, %xmm1
 ; X86-NEXT:    movdqa %xmm0, %xmm2
 ; X86-NEXT:    punpckhbw {{.*#+}} xmm2 = xmm2[8],xmm1[8],xmm2[9],xmm1[9],xmm2[10],xmm1[10],xmm2[11],xmm1[11],xmm2[12],xmm1[12],xmm2[13],xmm1[13],xmm2[14],xmm1[14],xmm2[15],xmm1[15]
@@ -79,7 +78,6 @@ define <4 x i32> @test_demandedbits_bitr
 ;
 ; X64-LABEL: test_demandedbits_bitreverse:
 ; X64:       # %bb.0:
-; X64-NEXT:    vpor {{.*}}(%rip), %xmm0, %xmm0
 ; X64-NEXT:    vpshufb {{.*#+}} xmm0 = xmm0[3,2,1,0,7,6,5,4,11,10,9,8,15,14,13,12]
 ; X64-NEXT:    vmovdqa {{.*#+}} xmm1 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
 ; X64-NEXT:    vpand %xmm1, %xmm0, %xmm2