[PATCH] D61830: [X86][SSE] Disable shouldFoldConstantShiftPairToMask for scalar shifts on AMD targets (PR40758)

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon created this revision.
RKSimon added reviewers: andreadb, spatel, lebedev.ri, craig.topper.
Herald added a project: LLVM.

D61068 <https://reviews.llvm.org/D61068> handled vector shifts, this patch does the same for scalars where there are similar number of pipes for shifts as bit ops.

This is true almost entirely for AMD targets where the scalar ALUs are well balanced

This combine avoids AND immediate mask which usually means we reduce encoding size.

Some tests show use of (slow, scaled) LEA instead of SHL in some cases, but thats due to particular shift immediates - shift+mask generate these just as easily.

NOTE: The tests show changes for (lshr (shl x, c1), c2) folds even though shouldFoldConstantShiftPairToMask isn't used yet because I've added new test targets - I'll fix that shortly.


Repository:
  rL LLVM

https://reviews.llvm.org/D61830

Files:
  lib/Target/X86/X86.td
  lib/Target/X86/X86ISelLowering.cpp
  lib/Target/X86/X86Subtarget.h
  test/CodeGen/X86/shift-mask.ll

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