[llvm] r360508 - gn build: sort tablegen rules for X86 and AArch64

[David L. Jones via llvm-commits]

Author: dlj
Date: Fri May 10 20:23:37 2019
New Revision: 360508

URL: http://llvm.org/viewvc/llvm-project?rev=360508&view=rev
Log:
gn build: sort tablegen rules for X86 and AArch64

Modified:
    llvm/trunk/utils/gn/secondary/llvm/lib/Target/AArch64/MCTargetDesc/BUILD.gn
    llvm/trunk/utils/gn/secondary/llvm/lib/Target/X86/MCTargetDesc/BUILD.gn

Modified: llvm/trunk/utils/gn/secondary/llvm/lib/Target/AArch64/MCTargetDesc/BUILD.gn
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/gn/secondary/llvm/lib/Target/AArch64/MCTargetDesc/BUILD.gn?rev=360508&r1=360507&r2=360508&view=diff
==============================================================================
--- llvm/trunk/utils/gn/secondary/llvm/lib/Target/AArch64/MCTargetDesc/BUILD.gn (original)
+++ llvm/trunk/utils/gn/secondary/llvm/lib/Target/AArch64/MCTargetDesc/BUILD.gn Fri May 10 20:23:37 2019
@@ -1,41 +1,41 @@
 import("//llvm/utils/TableGen/tablegen.gni")
 
-tablegen("AArch64GenInstrInfo") {
+tablegen("AArch64GenAsmWriter") {
   visibility = [ ":tablegen" ]
-  args = [ "-gen-instr-info" ]
+  args = [ "-gen-asm-writer" ]
   td_file = "../AArch64.td"
 }
 
-tablegen("AArch64GenMCCodeEmitter") {
+tablegen("AArch64GenAsmWriter1") {
   visibility = [ ":tablegen" ]
-  args = [ "-gen-emitter" ]
+  args = [
+    "-gen-asm-writer",
+    "-asmwriternum=1",
+  ]
   td_file = "../AArch64.td"
 }
 
-tablegen("AArch64GenRegisterInfo") {
+tablegen("AArch64GenInstrInfo") {
   visibility = [ ":tablegen" ]
-  args = [ "-gen-register-info" ]
+  args = [ "-gen-instr-info" ]
   td_file = "../AArch64.td"
 }
 
-tablegen("AArch64GenSubtargetInfo") {
+tablegen("AArch64GenMCCodeEmitter") {
   visibility = [ ":tablegen" ]
-  args = [ "-gen-subtarget" ]
+  args = [ "-gen-emitter" ]
   td_file = "../AArch64.td"
 }
 
-tablegen("AArch64GenAsmWriter") {
+tablegen("AArch64GenRegisterInfo") {
   visibility = [ ":tablegen" ]
-  args = [ "-gen-asm-writer" ]
+  args = [ "-gen-register-info" ]
   td_file = "../AArch64.td"
 }
 
-tablegen("AArch64GenAsmWriter1") {
+tablegen("AArch64GenSubtargetInfo") {
   visibility = [ ":tablegen" ]
-  args = [
-    "-gen-asm-writer",
-    "-asmwriternum=1",
-  ]
+  args = [ "-gen-subtarget" ]
   td_file = "../AArch64.td"
 }
 

Modified: llvm/trunk/utils/gn/secondary/llvm/lib/Target/X86/MCTargetDesc/BUILD.gn
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/gn/secondary/llvm/lib/Target/X86/MCTargetDesc/BUILD.gn?rev=360508&r1=360507&r2=360508&view=diff
==============================================================================
--- llvm/trunk/utils/gn/secondary/llvm/lib/Target/X86/MCTargetDesc/BUILD.gn (original)
+++ llvm/trunk/utils/gn/secondary/llvm/lib/Target/X86/MCTargetDesc/BUILD.gn Fri May 10 20:23:37 2019
@@ -1,35 +1,35 @@
 import("//llvm/utils/TableGen/tablegen.gni")
 
-tablegen("X86GenInstrInfo") {
+tablegen("X86GenAsmWriter") {
   visibility = [ ":tablegen" ]
-  args = [ "-gen-instr-info" ]
+  args = [ "-gen-asm-writer" ]
   td_file = "../X86.td"
 }
 
-tablegen("X86GenRegisterInfo") {
+tablegen("X86GenAsmWriter1") {
   visibility = [ ":tablegen" ]
-  args = [ "-gen-register-info" ]
+  args = [
+    "-gen-asm-writer",
+    "-asmwriternum=1",
+  ]
   td_file = "../X86.td"
 }
 
-tablegen("X86GenSubtargetInfo") {
+tablegen("X86GenInstrInfo") {
   visibility = [ ":tablegen" ]
-  args = [ "-gen-subtarget" ]
+  args = [ "-gen-instr-info" ]
   td_file = "../X86.td"
 }
 
-tablegen("X86GenAsmWriter") {
+tablegen("X86GenRegisterInfo") {
   visibility = [ ":tablegen" ]
-  args = [ "-gen-asm-writer" ]
+  args = [ "-gen-register-info" ]
   td_file = "../X86.td"
 }
 
-tablegen("X86GenAsmWriter1") {
+tablegen("X86GenSubtargetInfo") {
   visibility = [ ":tablegen" ]
-  args = [
-    "-gen-asm-writer",
-    "-asmwriternum=1",
-  ]
+  args = [ "-gen-subtarget" ]
   td_file = "../X86.td"
 }