[PATCH] D61528: Revert "[AMDGPU] Enable code selection using `s_mul_hi_u32`/`s_mul_hi_i32`."

[Konstantin Zhuravlyov via Phabricator via llvm-commits]

kzhuravl updated this revision to Diff 199091.
kzhuravl marked 2 inline comments as done.
kzhuravl added a comment.

Address review feedback.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D61528/new/

https://reviews.llvm.org/D61528

Files:
  lib/Target/AMDGPU/SOPInstructions.td
  test/CodeGen/AMDGPU/mul.ll


Index: test/CodeGen/AMDGPU/mul.ll
===================================================================
--- test/CodeGen/AMDGPU/mul.ll
+++ test/CodeGen/AMDGPU/mul.ll
@@ -141,11 +141,6 @@
 ; crash with a 'failed to select' error.
 
 ; FUNC-LABEL: {{^}}s_mul_i64:
-; GFX9_10-DAG: s_mul_i32
-; GFX9_10-DAG: s_mul_hi_u32
-; GFX9_10-DAG: s_mul_i32
-; GFX9_10-DAG: s_mul_i32
-; GFX9_10: s_endpgm
 define amdgpu_kernel void @s_mul_i64(i64 addrspace(1)* %out, i64 %a, i64 %b) nounwind {
   %mul = mul i64 %a, %b
   store i64 %mul, i64 addrspace(1)* %out, align 8
Index: lib/Target/AMDGPU/SOPInstructions.td
===================================================================
--- lib/Target/AMDGPU/SOPInstructions.td
+++ lib/Target/AMDGPU/SOPInstructions.td
@@ -558,12 +558,8 @@
     def S_LSHL4_ADD_U32 : SOP2_32<"s_lshl4_add_u32">;
   } // End Defs = [SCC]
 
-  let isCommutable = 1 in {
-    def S_MUL_HI_U32 : SOP2_32<"s_mul_hi_u32",
-      [(set i32:$sdst, (UniformBinFrag<mulhu> SSrc_b32:$src0, SSrc_b32:$src1))]>;
-    def S_MUL_HI_I32 : SOP2_32<"s_mul_hi_i32",
-      [(set i32:$sdst, (UniformBinFrag<mulhs> SSrc_b32:$src0, SSrc_b32:$src1))]>;
-  }
+  def S_MUL_HI_U32 : SOP2_32<"s_mul_hi_u32">;
+  def S_MUL_HI_I32 : SOP2_32<"s_mul_hi_i32">;
 } // End SubtargetPredicate = isGFX9Plus
 
 //===----------------------------------------------------------------------===//


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