[PATCH] D58632: [X86] Improve lowering of idemptotent RMW operations

[Philip Reames via llvm-commits]

Craig, if we have a base register, you probably need to extend that
check to RBP as well. 

Philip

On 5/10/19 12:22 PM, Craig Topper via Phabricator wrote:
> craig.topper added a comment.
>
> @sammccall, can you try this patch
>
>   diff --git a/llvm/lib/Target/X86/X86SpeculativeLoadHardening.cpp b/llvm/lib/Target/X86/X86SpeculativeLoadHardening.cpp
>   index c8b740ca39e..ab8cb5250c9 100644
>   --- a/llvm/lib/Target/X86/X86SpeculativeLoadHardening.cpp
>   +++ b/llvm/lib/Target/X86/X86SpeculativeLoadHardening.cpp
>   @@ -1958,7 +1958,7 @@ void X86SpeculativeLoadHardeningPass::hardenLoadAddr(
>    
>      SmallVector<MachineOperand *, 2> HardenOpRegs;
>    
>   -  if (BaseMO.isFI()) {
>   +  if (BaseMO.isFI() || BaseMO.getReg() == X86::RSP) {
>        // A frame index is never a dynamically controllable load, so only
>        // harden it if we're covering fixed address loads as well.
>        LLVM_DEBUG(
>
>
> Repository:
>   rL LLVM
>
> CHANGES SINCE LAST ACTION
>   https://reviews.llvm.org/D58632/new/
>
> https://reviews.llvm.org/D58632
>
>
>