[PATCH] D61658: [PowerPC] Emit XXSEL for vec_sel and code that has the same pattern

[Jinsong Ji via Phabricator via llvm-commits]

jsji added a comment.

Have we thought about adding support in DAGCombine  or even InstCombine to combine into  `ISD::VSELECT` too?



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Comment at: lib/Target/PowerPC/PPCInstrVSX.td:964
+          (v4i32 (XXSEL $A, $B, $C))>;
+def : Pat<(v4i32 (or (and v4i32:$A, (vnot_ppc v4i32:$C)),
+                     (and v4i32:$B, v4i32:$C))),
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Why we need this pattern? `and` should be a commutable op?


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Comment at: test/CodeGen/PowerPC/vec-select.ll:24
+  %neg.i = xor <8 x i16> %c, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>
+  %and.i = and <8 x i16> %neg.i, %a
+  %and1.i = and <8 x i16> %c, %b
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I think it would be better if we swap `%neg.i, %a` to test commutable patterns.


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Comment at: test/CodeGen/PowerPC/vec-select.ll:26
+  %and1.i = and <8 x i16> %c, %b
+  %or.i = or <8 x i16> %and.i, %and1.i
+  ret <8 x i16> %or.i
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I think it would be better if we swap `%and.i, %and1.i` to test commutable patterns.


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Comment at: test/CodeGen/PowerPC/vec-select.ll:41
+  ret <16 x i8> %or.i
+}
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How about  adding a test of <2 x i64> for vector double too?
And maybe <4 x i1> as a negative test?


Repository:
  rL LLVM

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  https://reviews.llvm.org/D61658/new/

https://reviews.llvm.org/D61658