[PATCH] D61020: [ARM][ParallelDSP] Relax alias checks

[Sam Parker via Phabricator via llvm-commits]

samparker updated this revision to Diff 198804.
samparker added a comment.

When we create a wide load, we pull the second load up to the first. So for aliasing worries, we only need to check whether there's a write between the two loads that would prevent us from hoisting the second load.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D61020/new/

https://reviews.llvm.org/D61020

Files:
  lib/Target/ARM/ARMParallelDSP.cpp
  test/CodeGen/ARM/ParallelDSP/aliasing.ll
  test/CodeGen/ARM/ParallelDSP/smlad0.ll
  test/CodeGen/ARM/ParallelDSP/smlad1.ll
  test/CodeGen/ARM/ParallelDSP/smlad11.ll
  test/CodeGen/ARM/ParallelDSP/smlad6.ll
  test/CodeGen/ARM/ParallelDSP/smlad7.ll
  test/CodeGen/ARM/ParallelDSP/smladx-1.ll
  test/CodeGen/ARM/ParallelDSP/smlald0.ll
  test/CodeGen/ARM/ParallelDSP/smlald1.ll
  test/CodeGen/ARM/ParallelDSP/smlald2.ll
  test/CodeGen/ARM/ParallelDSP/smlaldx-1.ll
  test/CodeGen/ARM/ParallelDSP/smlaldx-2.ll

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