[llvm] r360300 - [AMDGPU] gfx1010 tests. NFC.
Stanislav Mekhanoshin via llvm-commits
llvm-commits at lists.llvm.org
Wed May 8 16:31:32 PDT 2019
Author: rampitec
Date: Wed May 8 16:31:32 2019
New Revision: 360300
URL: http://llvm.org/viewvc/llvm-project?rev=360300&view=rev
Log:
[AMDGPU] gfx1010 tests. NFC.
Added tests which now pass after code commits.
Added:
llvm/trunk/test/MC/AMDGPU/gfx9-vop2be-literal.s
llvm/trunk/test/MC/AMDGPU/vcmpx-gfx10.s
llvm/trunk/test/MC/Disassembler/AMDGPU/vcmpx-gfx10.txt
Modified:
llvm/trunk/test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.load.ll
llvm/trunk/test/CodeGen/AMDGPU/llvm.amdgcn.raw.tbuffer.load.ll
llvm/trunk/test/MC/AMDGPU/sopp-gfx9.s
llvm/trunk/test/MC/AMDGPU/xnack-mask.s
Modified: llvm/trunk/test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.load.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.load.ll?rev=360300&r1=360299&r2=360300&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.load.ll (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.load.ll Wed May 8 16:31:32 2019
@@ -1,10 +1,11 @@
-;RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck %s -check-prefix=CHECK -check-prefix=SICI
-;RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s -check-prefix=CHECK -check-prefix=VI
+;RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck %s -check-prefix=CHECK -check-prefixes=SICI,PREGFX10
+;RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s -check-prefix=CHECK -check-prefixes=VI,PREGFX10
+;RUN: llc < %s -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs | FileCheck %s -check-prefix=CHECK -check-prefix=GFX10
;CHECK-LABEL: {{^}}buffer_load:
-;CHECK: buffer_load_dwordx4 v[0:3], off, s[0:3], 0
-;CHECK: buffer_load_dwordx4 v[4:7], off, s[0:3], 0 glc
-;CHECK: buffer_load_dwordx4 v[8:11], off, s[0:3], 0 slc
+;CHECK: buffer_load_dwordx4 v[0:3], off, s[0:3], 0{{$}}
+;CHECK: buffer_load_dwordx4 v[4:7], off, s[0:3], 0 glc{{$}}
+;CHECK: buffer_load_dwordx4 v[8:11], off, s[0:3], 0 slc{{$}}
;CHECK: s_waitcnt
define amdgpu_ps {<4 x float>, <4 x float>, <4 x float>} @buffer_load(<4 x i32> inreg) {
main_body:
@@ -17,6 +18,25 @@ main_body:
ret {<4 x float>, <4 x float>, <4 x float>} %r2
}
+;CHECK-LABEL: {{^}}buffer_load_dlc:
+;PREGFX10: buffer_load_dwordx4 v[0:3], off, s[0:3], 0{{$}}
+;PREGFX10: buffer_load_dwordx4 v[4:7], off, s[0:3], 0 glc{{$}}
+;PREGFX10: buffer_load_dwordx4 v[8:11], off, s[0:3], 0 slc{{$}}
+;GFX10: buffer_load_dwordx4 v[0:3], off, s[0:3], 0 dlc{{$}}
+;GFX10: buffer_load_dwordx4 v[4:7], off, s[0:3], 0 glc dlc{{$}}
+;GFX10: buffer_load_dwordx4 v[8:11], off, s[0:3], 0 slc dlc{{$}}
+;CHECK: s_waitcnt
+define amdgpu_ps {<4 x float>, <4 x float>, <4 x float>} @buffer_load_dlc(<4 x i32> inreg) {
+main_body:
+ %data = call <4 x float> @llvm.amdgcn.raw.buffer.load.v4f32(<4 x i32> %0, i32 0, i32 0, i32 4)
+ %data_glc = call <4 x float> @llvm.amdgcn.raw.buffer.load.v4f32(<4 x i32> %0, i32 0, i32 0, i32 5)
+ %data_slc = call <4 x float> @llvm.amdgcn.raw.buffer.load.v4f32(<4 x i32> %0, i32 0, i32 0, i32 6)
+ %r0 = insertvalue {<4 x float>, <4 x float>, <4 x float>} undef, <4 x float> %data, 0
+ %r1 = insertvalue {<4 x float>, <4 x float>, <4 x float>} %r0, <4 x float> %data_glc, 1
+ %r2 = insertvalue {<4 x float>, <4 x float>, <4 x float>} %r1, <4 x float> %data_slc, 2
+ ret {<4 x float>, <4 x float>, <4 x float>} %r2
+}
+
;CHECK-LABEL: {{^}}buffer_load_immoffs:
;CHECK: buffer_load_dwordx4 v[0:3], off, s[0:3], 0 offset:40
;CHECK: s_waitcnt
@@ -74,7 +94,8 @@ main_body:
}
;CHECK-LABEL: {{^}}buffer_load_negative_offset:
-;CHECK: v_add_{{[iu]}}32_e32 [[VOFS:v[0-9]+]], vcc, -16, v0
+;PREGFX10: v_add_{{[iu]}}32_e32 [[VOFS:v[0-9]+]], vcc, -16, v0
+;GFX10: v_add_nc_{{[iu]}}32_e32 [[VOFS:v[0-9]+]], -16, v0
;CHECK: buffer_load_dwordx4 v[0:3], [[VOFS]], s[0:3], 0 offen
define amdgpu_ps <4 x float> @buffer_load_negative_offset(<4 x i32> inreg, i32 %ofs) {
main_body:
@@ -280,7 +301,7 @@ main_body:
;CHECK-LABEL: {{^}}raw_buffer_load_ushort:
;CHECK-NEXT: %bb.
;CHECK-NEXT: buffer_load_ushort v{{[0-9]}}, off, s[0:3], 0
-;CHECK-NEXT: s_waitcnt vmcnt(0)
+;CHECK: s_waitcnt vmcnt(0)
;CHECK-NEXT: v_cvt_f32_u32_e32 v0, v0
;CHECK-NEXT: ; return to shader part epilog
define amdgpu_ps float @raw_buffer_load_ushort(<4 x i32> inreg %rsrc) {
@@ -294,7 +315,7 @@ main_body:
;CHECK-LABEL: {{^}}raw_buffer_load_sbyte:
;CHECK-NEXT: %bb.
;CHECK-NEXT: buffer_load_sbyte v{{[0-9]}}, off, s[0:3], 0
-;CHECK-NEXT: s_waitcnt vmcnt(0)
+;CHECK: s_waitcnt vmcnt(0)
;CHECK-NEXT: v_cvt_f32_i32_e32 v0, v0
;CHECK-NEXT: ; return to shader part epilog
define amdgpu_ps float @raw_buffer_load_sbyte(<4 x i32> inreg %rsrc) {
@@ -308,7 +329,7 @@ main_body:
;CHECK-LABEL: {{^}}raw_buffer_load_sshort:
;CHECK-NEXT: %bb.
;CHECK-NEXT: buffer_load_sshort v{{[0-9]}}, off, s[0:3], 0
-;CHECK-NEXT: s_waitcnt vmcnt(0)
+;CHECK: s_waitcnt vmcnt(0)
;CHECK-NEXT: v_cvt_f32_i32_e32 v0, v0
;CHECK-NEXT: ; return to shader part epilog
define amdgpu_ps float @raw_buffer_load_sshort(<4 x i32> inreg %rsrc) {
Modified: llvm/trunk/test/CodeGen/AMDGPU/llvm.amdgcn.raw.tbuffer.load.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/llvm.amdgcn.raw.tbuffer.load.ll?rev=360300&r1=360299&r2=360300&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/llvm.amdgcn.raw.tbuffer.load.ll (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/llvm.amdgcn.raw.tbuffer.load.ll Wed May 8 16:31:32 2019
@@ -1,18 +1,23 @@
-;RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck -check-prefix=GCN %s
-;RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck -check-prefix=GCN %s
+;RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck -check-prefix=GCN -check-prefix=PREGFX10 %s
+;RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck -check-prefix=GCN -check-prefix=PREGFX10 %s
+;RUN: llc < %s -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs | FileCheck -check-prefix=GCN -check-prefix=GFX10 %s
; GCN-LABEL: {{^}}tbuffer_load:
-; GCN: tbuffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, off, {{s\[[0-9]+:[0-9]+\]}}, dfmt:14, nfmt:4, 0
-; GCN: tbuffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, off, {{s\[[0-9]+:[0-9]+\]}}, dfmt:15, nfmt:3, 0 glc
-; GCN: tbuffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, off, {{s\[[0-9]+:[0-9]+\]}}, dfmt:6, nfmt:1, 0 slc
-; GCN: tbuffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, off, {{s\[[0-9]+:[0-9]+\]}}, dfmt:6, nfmt:1, 0
+; PREGFX10: tbuffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, off, {{s\[[0-9]+:[0-9]+\]}}, dfmt:14, nfmt:4, 0
+; PREGFX10: tbuffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, off, {{s\[[0-9]+:[0-9]+\]}}, dfmt:15, nfmt:3, 0 glc
+; PREGFX10: tbuffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, off, {{s\[[0-9]+:[0-9]+\]}}, dfmt:6, nfmt:1, 0 slc
+; PREGFX10: tbuffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, off, {{s\[[0-9]+:[0-9]+\]}}, dfmt:6, nfmt:1, 0 glc
+; GFX10-DAG: tbuffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, off, {{s\[[0-9]+:[0-9]+\]}}, format:78, 0
+; GFX10-DAG: tbuffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, off, {{s\[[0-9]+:[0-9]+\]}}, format:63, 0 glc
+; GFX10-DAG: tbuffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, off, {{s\[[0-9]+:[0-9]+\]}}, format:22, 0 slc
+; GFX10-DAG: tbuffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, off, {{s\[[0-9]+:[0-9]+\]}}, format:22, 0 glc dlc
; GCN: s_waitcnt
define amdgpu_vs {<4 x float>, <4 x float>, <4 x float>, <4 x float>} @tbuffer_load(<4 x i32> inreg) {
main_body:
%vdata = call <4 x i32> @llvm.amdgcn.raw.tbuffer.load.v4i32(<4 x i32> %0, i32 0, i32 0, i32 78, i32 0)
%vdata_glc = call <4 x i32> @llvm.amdgcn.raw.tbuffer.load.v4i32(<4 x i32> %0, i32 0, i32 0, i32 63, i32 1)
%vdata_slc = call <4 x i32> @llvm.amdgcn.raw.tbuffer.load.v4i32(<4 x i32> %0, i32 0, i32 0, i32 22, i32 2)
- %vdata_f32 = call <4 x float> @llvm.amdgcn.raw.tbuffer.load.v4f32(<4 x i32> %0, i32 0, i32 0, i32 22, i32 0)
+ %vdata_f32 = call <4 x float> @llvm.amdgcn.raw.tbuffer.load.v4f32(<4 x i32> %0, i32 0, i32 0, i32 22, i32 5)
%vdata.f = bitcast <4 x i32> %vdata to <4 x float>
%vdata_glc.f = bitcast <4 x i32> %vdata_glc to <4 x float>
%vdata_slc.f = bitcast <4 x i32> %vdata_slc to <4 x float>
@@ -24,7 +29,8 @@ main_body:
}
; GCN-LABEL: {{^}}tbuffer_load_immoffs:
-; GCN: tbuffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, off, {{s\[[0-9]+:[0-9]+\]}}, dfmt:14, nfmt:4, 0 offset:42
+; PREGFX10: tbuffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, off, {{s\[[0-9]+:[0-9]+\]}}, dfmt:14, nfmt:4, 0 offset:42
+; GFX10: tbuffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, off, {{s\[[0-9]+:[0-9]+\]}}, format:78, 0 offset:42
define amdgpu_vs <4 x float> @tbuffer_load_immoffs(<4 x i32> inreg) {
main_body:
%vdata = call <4 x i32> @llvm.amdgcn.raw.tbuffer.load.v4i32(<4 x i32> %0, i32 42, i32 0, i32 78, i32 0)
@@ -33,9 +39,12 @@ main_body:
}
; GCN-LABEL: {{^}}tbuffer_load_immoffs_large
-; GCN: tbuffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, off, {{s\[[0-9]+:[0-9]+\]}}, dfmt:15, nfmt:2, 61 offset:4095
-; GCN: tbuffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, off, {{s\[[0-9]+:[0-9]+\]}}, dfmt:14, nfmt:3, {{s[0-9]+}} offset:73
-; GCN: tbuffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, off, {{s\[[0-9]+:[0-9]+\]}}, dfmt:13, nfmt:4, {{s[0-9]+}} offset:1
+; PREGFX10: tbuffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, off, {{s\[[0-9]+:[0-9]+\]}}, dfmt:15, nfmt:2, 61 offset:4095
+; PREGFX10: tbuffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, off, {{s\[[0-9]+:[0-9]+\]}}, dfmt:14, nfmt:3, {{s[0-9]+}} offset:73
+; PREGFX10: tbuffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, off, {{s\[[0-9]+:[0-9]+\]}}, dfmt:13, nfmt:4, {{s[0-9]+}} offset:1
+; GFX10-DAG: tbuffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, off, {{s\[[0-9]+:[0-9]+\]}}, format:47, 61 offset:4095
+; GFX10-DAG: tbuffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, off, {{s\[[0-9]+:[0-9]+\]}}, format:62, {{s[0-9]+}} offset:73
+; GFX10-DAG: tbuffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, off, {{s\[[0-9]+:[0-9]+\]}}, format:77, {{s[0-9]+}} offset:1
; GCN: s_waitcnt
define amdgpu_vs {<4 x float>, <4 x float>, <4 x float>} @tbuffer_load_immoffs_large(<4 x i32> inreg, i32 inreg %soffs) {
%vdata = call <4 x i32> @llvm.amdgcn.raw.tbuffer.load.v4i32(<4 x i32> %0, i32 4095, i32 61, i32 47, i32 0)
@@ -51,7 +60,8 @@ define amdgpu_vs {<4 x float>, <4 x floa
}
; GCN-LABEL: {{^}}tbuffer_load_ofs:
-; GCN: tbuffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, dfmt:14, nfmt:4, 0 offen
+; PREGFX10: tbuffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, dfmt:14, nfmt:4, 0 offen
+; GFX10: tbuffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, format:78, 0 offen
define amdgpu_vs <4 x float> @tbuffer_load_ofs(<4 x i32> inreg, i32 %voffs) {
main_body:
%vdata = call <4 x i32> @llvm.amdgcn.raw.tbuffer.load.v4i32(<4 x i32> %0, i32 %voffs, i32 0, i32 78, i32 0)
@@ -60,7 +70,8 @@ main_body:
}
; GCN-LABEL: {{^}}tbuffer_load_ofs_imm:
-; GCN: tbuffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, dfmt:14, nfmt:4, 0 offen offset:52
+; PREGFX10: tbuffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, dfmt:14, nfmt:4, 0 offen offset:52
+; GFX10: tbuffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, format:78, 0 offen offset:52
define amdgpu_vs <4 x float> @tbuffer_load_ofs_imm(<4 x i32> inreg, i32 %voffs) {
main_body:
%ofs = add i32 %voffs, 52
@@ -70,7 +81,8 @@ main_body:
}
; GCN-LABEL: {{^}}buffer_load_xy:
-; GCN: tbuffer_load_format_xy {{v\[[0-9]+:[0-9]+\]}}, off, {{s\[[0-9]+:[0-9]+\]}}, dfmt:13, nfmt:4, 0
+; PREGFX10: tbuffer_load_format_xy {{v\[[0-9]+:[0-9]+\]}}, off, {{s\[[0-9]+:[0-9]+\]}}, dfmt:13, nfmt:4, 0
+; GFX10: tbuffer_load_format_xy {{v\[[0-9]+:[0-9]+\]}}, off, {{s\[[0-9]+:[0-9]+\]}}, format:77, 0
define amdgpu_vs <2 x float> @buffer_load_xy(<4 x i32> inreg %rsrc) {
%vdata = call <2 x i32> @llvm.amdgcn.raw.tbuffer.load.v2i32(<4 x i32> %rsrc, i32 0, i32 0, i32 77, i32 0)
%vdata.f = bitcast <2 x i32> %vdata to <2 x float>
@@ -78,7 +90,8 @@ define amdgpu_vs <2 x float> @buffer_loa
}
; GCN-LABEL: {{^}}buffer_load_x:
-; GCN: tbuffer_load_format_x {{v[0-9]+}}, off, {{s\[[0-9]+:[0-9]+\]}}, dfmt:13, nfmt:4, 0
+; PREGFX10: tbuffer_load_format_x {{v[0-9]+}}, off, {{s\[[0-9]+:[0-9]+\]}}, dfmt:13, nfmt:4, 0
+; GFX10: tbuffer_load_format_x {{v[0-9]+}}, off, {{s\[[0-9]+:[0-9]+\]}}, format:77, 0
define amdgpu_vs float @buffer_load_x(<4 x i32> inreg %rsrc) {
%vdata = call i32 @llvm.amdgcn.raw.tbuffer.load.i32(<4 x i32> %rsrc, i32 0, i32 0, i32 77, i32 0)
%vdata.f = bitcast i32 %vdata to float
Added: llvm/trunk/test/MC/AMDGPU/gfx9-vop2be-literal.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AMDGPU/gfx9-vop2be-literal.s?rev=360300&view=auto
==============================================================================
--- llvm/trunk/test/MC/AMDGPU/gfx9-vop2be-literal.s (added)
+++ llvm/trunk/test/MC/AMDGPU/gfx9-vop2be-literal.s Wed May 8 16:31:32 2019
@@ -0,0 +1,7 @@
+# RUN: not llvm-mc -arch=amdgcn -mcpu=gfx900 -show-encoding < %s 2>&1 | FileCheck -check-prefix=GFX9-ERR %s
+
+v_addc_co_u32_e32 v3, vcc, 12345, v3, vcc
+// GFX9-ERR: error: invalid operand (violates constant bus restrictions)
+
+v_cndmask_b32 v0, 12345, v1, vcc
+// GFX9-ERR: error: invalid operand (violates constant bus restrictions)
Modified: llvm/trunk/test/MC/AMDGPU/sopp-gfx9.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AMDGPU/sopp-gfx9.s?rev=360300&r1=360299&r2=360300&view=diff
==============================================================================
--- llvm/trunk/test/MC/AMDGPU/sopp-gfx9.s (original)
+++ llvm/trunk/test/MC/AMDGPU/sopp-gfx9.s Wed May 8 16:31:32 2019
@@ -69,3 +69,9 @@ s_waitcnt vmcnt(62) lgkmcnt(14)
s_waitcnt vmcnt(62) expcnt(6) lgkmcnt(14)
// GFX9: s_waitcnt vmcnt(62) expcnt(6) lgkmcnt(14) ; encoding: [0x6e,0xce,0x8c,0xbf]
+
+s_sendmsg 9
+// GCN: s_sendmsg sendmsg(MSG_GS_ALLOC_REQ) ; encoding: [0x09,0x00,0x90,0xbf]
+
+s_sendmsg sendmsg(MSG_GS_ALLOC_REQ)
+// GFX9: s_sendmsg sendmsg(MSG_GS_ALLOC_REQ) ; encoding: [0x09,0x00,0x90,0xbf]
Added: llvm/trunk/test/MC/AMDGPU/vcmpx-gfx10.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AMDGPU/vcmpx-gfx10.s?rev=360300&view=auto
==============================================================================
--- llvm/trunk/test/MC/AMDGPU/vcmpx-gfx10.s (added)
+++ llvm/trunk/test/MC/AMDGPU/vcmpx-gfx10.s Wed May 8 16:31:32 2019
@@ -0,0 +1,40 @@
+// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1010 -show-encoding < %s | FileCheck -check-prefix=GFX10 %s
+
+// GFX10: v_cmpx_le_f32_e64 v1, v0 ; encoding: [0x00,0x00,0x13,0xd4,0x01,0x01,0x02,0x00]
+v_cmpx_le_f32_e64 v1, v0
+
+// GFX10: v_cmpx_le_f32_e64 -|v1|, v0 ; encoding: [0x00,0x01,0x13,0xd4,0x01,0x01,0x02,0x20]
+v_cmpx_le_f32_e64 -|v1|, v0
+
+// GFX10: v_cmpx_le_f32_e64 -|v1|, v0 ; encoding: [0x00,0x01,0x13,0xd4,0x01,0x01,0x02,0x20]
+v_cmpx_le_f32 -|v1|, v0
+
+// GFX10: v_cmpx_le_f32_e64 -|v1|, v0 clamp ; encoding: [0x00,0x81,0x13,0xd4,0x01,0x01,0x02,0x20]
+v_cmpx_le_f32 -|v1|, v0 clamp
+
+// GFX10: v_cmpx_le_f32_e32 v1, v0 ; encoding: [0x01,0x01,0x26,0x7c]
+v_cmpx_le_f32 v1, v0
+
+// GFX10: v_cmpx_le_f32_e32 v1, v0 ; encoding: [0x01,0x01,0x26,0x7c]
+v_cmpx_le_f32_e32 v1, v0
+
+// GFX10: v_cmpx_le_u32_e32 0, v0 ; encoding: [0x80,0x00,0xa6,0x7d]
+v_cmpx_le_u32 0, v0
+
+// GFX10: v_cmpx_le_u32_e32 0, v0 ; encoding: [0x80,0x00,0xa6,0x7d]
+v_cmpx_le_u32_e32 0, v0
+
+// GFX10: v_cmpx_le_u32_e64 0, v0 ; encoding: [0x00,0x00,0xd3,0xd4,0x80,0x00,0x02,0x00]
+v_cmpx_le_u32_e64 0, v0
+
+// GFX10: v_cmpx_le_f16_sdwa v3, v4 src0_sel:WORD_1 src1_sel:DWORD ; encoding: [0xf9,0x08,0xb6,0x7d,0x03,0x00,0x05,0x06]
+v_cmpx_le_f16_sdwa v3, v4 src0_sel:WORD_1 src1_sel:DWORD
+
+// GFX10: v_cmpx_le_f16_sdwa v3, v4 src0_sel:WORD_1 src1_sel:DWORD ; encoding: [0xf9,0x08,0xb6,0x7d,0x03,0x00,0x05,0x06]
+v_cmpx_le_f16 v3, v4 src0_sel:WORD_1 src1_sel:DWORD
+
+// GFX10: v_cmpx_class_f32_e64 v0, 1 ; encoding: [0x00,0x00,0x98,0xd4,0x00,0x03,0x01,0x00]
+v_cmpx_class_f32 v0, 1
+
+// GFX10: v_cmpx_class_f32_e64 v0, 1 ; encoding: [0x00,0x00,0x98,0xd4,0x00,0x03,0x01,0x00]
+v_cmpx_class_f32_e64 v0, 1
Modified: llvm/trunk/test/MC/AMDGPU/xnack-mask.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AMDGPU/xnack-mask.s?rev=360300&r1=360299&r2=360300&view=diff
==============================================================================
--- llvm/trunk/test/MC/AMDGPU/xnack-mask.s (original)
+++ llvm/trunk/test/MC/AMDGPU/xnack-mask.s Wed May 8 16:31:32 2019
@@ -1,30 +1,31 @@
-// RUN: not llvm-mc -arch=amdgcn -mcpu=tahiti -show-encoding %s 2>&1 | FileCheck -check-prefix=NOSICIVI %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=hawaii -show-encoding %s 2>&1 | FileCheck -check-prefix=NOSICIVI %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s 2>&1 | FileCheck -check-prefix=NOSICIVI %s
+// RUN: not llvm-mc -arch=amdgcn -mcpu=tahiti -show-encoding %s 2>&1 | FileCheck -check-prefix=NOSICIVI10 %s
+// RUN: not llvm-mc -arch=amdgcn -mcpu=hawaii -show-encoding %s 2>&1 | FileCheck -check-prefix=NOSICIVI10 %s
+// RUN: not llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s 2>&1 | FileCheck -check-prefix=NOSICIVI10 %s
+// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1001 -show-encoding %s 2>&1 | FileCheck -check-prefix=NOSICIVI10 %s
// RUN: not llvm-mc -arch=amdgcn -mcpu=stoney -show-encoding %s 2>&1 | FileCheck -check-prefix=XNACKERR %s
// RUN: not llvm-mc -arch=amdgcn -mcpu=stoney -show-encoding %s | FileCheck -check-prefix=XNACK %s
s_mov_b64 xnack_mask, -1
-// NOSICIVI: error: not a valid operand.
+// NOSICIVI10: error: not a valid operand.
// XNACK: s_mov_b64 xnack_mask, -1 ; encoding: [0xc1,0x01,0xe8,0xbe]
s_mov_b32 xnack_mask_lo, -1
-// NOSICIVI: error: not a valid operand.
+// NOSICIVI10: error: not a valid operand.
// XNACK: s_mov_b32 xnack_mask_lo, -1 ; encoding: [0xc1,0x00,0xe8,0xbe]
s_mov_b32 xnack_mask_hi, -1
-// NOSICIVI: error: not a valid operand.
+// NOSICIVI10: error: not a valid operand.
// XNACK: s_mov_b32 xnack_mask_hi, -1 ; encoding: [0xc1,0x00,0xe9,0xbe]
s_mov_b32 xnack_mask, -1
-// NOSICIVI: error: not a valid operand.
+// NOSICIVI10: error: not a valid operand.
// XNACKERR: error: invalid operand for instruction
s_mov_b64 xnack_mask_lo, -1
-// NOSICIVI: error: not a valid operand.
+// NOSICIVI10: error: not a valid operand.
// XNACKERR: error: invalid operand for instruction
s_mov_b64 xnack_mask_hi, -1
-// NOSICIVI: error: not a valid operand.
+// NOSICIVI10: error: not a valid operand.
// XNACKERR: error: invalid operand for instruction
Added: llvm/trunk/test/MC/Disassembler/AMDGPU/vcmpx-gfx10.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/AMDGPU/vcmpx-gfx10.txt?rev=360300&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/AMDGPU/vcmpx-gfx10.txt (added)
+++ llvm/trunk/test/MC/Disassembler/AMDGPU/vcmpx-gfx10.txt Wed May 8 16:31:32 2019
@@ -0,0 +1,36 @@
+# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1010 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX10 %s
+
+#===------------------------------------------------------------------------===#
+# Regular v_cmpx encoding
+#===------------------------------------------------------------------------===#
+
+# GFX10: v_cmpx_eq_f16_e64 s1, v2
+0x00,0x00,0xda,0xd4,0x01,0x04,0x02,0x00
+
+# GFX10: v_cmpx_class_f32_e64 v0, 1
+0x00,0x00,0x98,0xd4,0x00,0x03,0x01,0x00
+
+# GFX10: v_cmpx_eq_f16_sdwa -v1, v2 src0_sel:DWORD src1_sel:DWORD
+0xf9,0x04,0xb4,0x7d,0x01,0x00,0x16,0x06
+
+# GFX10: v_cmpx_class_f32_sdwa v0, 1 src0_sel:WORD_1 src1_sel:DWORD
+0xf9,0x02,0x31,0x7d,0x00,0x00,0x05,0x86
+
+#===------------------------------------------------------------------------===#
+# v_cmpx with arbitrary DST value should also be decodable
+#===------------------------------------------------------------------------===#
+
+# GFX10: v_cmpx_eq_f16_e64 s1, v2
+0x7e,0x00,0xda,0xd4,0x01,0x04,0x02,0x00
+
+# GFX10: v_cmpx_class_f32_e64 v0, 1
+0x7e,0x00,0x98,0xd4,0x00,0x03,0x01,0x00
+
+# GFX10: v_cmpx_eq_f16_sdwa -v1, v2 src0_sel:DWORD src1_sel:DWORD
+0xf9,0x04,0xb4,0x7d,0x01,0x7e,0x16,0x06
+
+# GFX10: v_cmpx_class_f32_sdwa v0, 1 src0_sel:WORD_1 src1_sel:DWORD
+0xf9,0x02,0x31,0x7d,0x00,0x7e,0x05,0x86
+
+# GFX10: v_cmpx_class_f32_sdwa v0, 1 src0_sel:WORD_1 src1_sel:DWORD
+0xf9,0x02,0x31,0x7d,0x00,0x7d,0x05,0x86
More information about the llvm-commits
mailing list