[llvm] r360296 - [SelectionDAG] fold 'fneg undef' to undef
Sanjay Patel via llvm-commits
llvm-commits at lists.llvm.org
Wed May 8 15:19:52 PDT 2019
Author: spatel
Date: Wed May 8 15:19:52 2019
New Revision: 360296
URL: http://llvm.org/viewvc/llvm-project?rev=360296&view=rev
Log:
[SelectionDAG] fold 'fneg undef' to undef
This is extracted from the original draft of D61419 with some additional tests.
We don't currently get this in IR (it's conservatively turned into a NaN),
but presumably that'll get updated as we add real IR support for 'fneg'
rather than 'fsub -0.0, x'.
The x86-32 run shows the following, and I haven't looked further to see why,
but that seems to be independent:
Legalizing: t1: f32 = undef
Trying to expand node
Creating fp constant: t4: f32 = ConstantFP<0.000000e+00>
Differential Revision: https://reviews.llvm.org/D61516
Modified:
llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
llvm/trunk/test/CodeGen/X86/vec_fneg.ll
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=360296&r1=360295&r2=360296&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Wed May 8 15:19:52 2019
@@ -4482,6 +4482,10 @@ SDValue SelectionDAG::getNode(unsigned O
return Operand.getOperand(0);
break;
case ISD::FNEG:
+ // Negation of an unknown bag of bits is still completely undefined.
+ if (OpOpcode == ISD::UNDEF)
+ return getUNDEF(VT);
+
// -(X-Y) -> (Y-X) is unsafe because when X==Y, -0.0 != +0.0
if ((getTarget().Options.UnsafeFPMath || Flags.hasNoSignedZeros()) &&
OpOpcode == ISD::FSUB)
Modified: llvm/trunk/test/CodeGen/X86/vec_fneg.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vec_fneg.ll?rev=360296&r1=360295&r2=360296&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/vec_fneg.ll (original)
+++ llvm/trunk/test/CodeGen/X86/vec_fneg.ll Wed May 8 15:19:52 2019
@@ -24,105 +24,51 @@ define <4 x float> @t1(<4 x float> %Q) n
; Possibly misplaced test, but since we're checking undef scenarios...
define float @scalar_fsub_neg0_undef(float %x) nounwind {
-; X32-SSE1-LABEL: scalar_fsub_neg0_undef:
-; X32-SSE1: # %bb.0:
-; X32-SSE1-NEXT: pushl %eax
-; X32-SSE1-NEXT: xorps {{\.LCPI.*}}, %xmm0
-; X32-SSE1-NEXT: movss %xmm0, (%esp)
-; X32-SSE1-NEXT: flds (%esp)
-; X32-SSE1-NEXT: popl %eax
-; X32-SSE1-NEXT: retl
-;
-; X32-SSE2-LABEL: scalar_fsub_neg0_undef:
-; X32-SSE2: # %bb.0:
-; X32-SSE2-NEXT: pushl %eax
-; X32-SSE2-NEXT: movss %xmm0, (%esp)
-; X32-SSE2-NEXT: flds (%esp)
-; X32-SSE2-NEXT: popl %eax
-; X32-SSE2-NEXT: retl
-;
-; X64-SSE1-LABEL: scalar_fsub_neg0_undef:
-; X64-SSE1: # %bb.0:
-; X64-SSE1-NEXT: xorps {{.*}}(%rip), %xmm0
-; X64-SSE1-NEXT: retq
-;
-; X64-SSE2-LABEL: scalar_fsub_neg0_undef:
-; X64-SSE2: # %bb.0:
-; X64-SSE2-NEXT: retq
+; X32-SSE-LABEL: scalar_fsub_neg0_undef:
+; X32-SSE: # %bb.0:
+; X32-SSE-NEXT: fldz
+; X32-SSE-NEXT: retl
+;
+; X64-SSE-LABEL: scalar_fsub_neg0_undef:
+; X64-SSE: # %bb.0:
+; X64-SSE-NEXT: retq
%r = fsub float -0.0, undef
ret float %r
}
define float @scalar_fneg_undef(float %x) nounwind {
-; X32-SSE1-LABEL: scalar_fneg_undef:
-; X32-SSE1: # %bb.0:
-; X32-SSE1-NEXT: pushl %eax
-; X32-SSE1-NEXT: xorps {{\.LCPI.*}}, %xmm0
-; X32-SSE1-NEXT: movss %xmm0, (%esp)
-; X32-SSE1-NEXT: flds (%esp)
-; X32-SSE1-NEXT: popl %eax
-; X32-SSE1-NEXT: retl
-;
-; X32-SSE2-LABEL: scalar_fneg_undef:
-; X32-SSE2: # %bb.0:
-; X32-SSE2-NEXT: pushl %eax
-; X32-SSE2-NEXT: movss %xmm0, (%esp)
-; X32-SSE2-NEXT: flds (%esp)
-; X32-SSE2-NEXT: popl %eax
-; X32-SSE2-NEXT: retl
-;
-; X64-SSE1-LABEL: scalar_fneg_undef:
-; X64-SSE1: # %bb.0:
-; X64-SSE1-NEXT: xorps {{.*}}(%rip), %xmm0
-; X64-SSE1-NEXT: retq
-;
-; X64-SSE2-LABEL: scalar_fneg_undef:
-; X64-SSE2: # %bb.0:
-; X64-SSE2-NEXT: retq
+; X32-SSE-LABEL: scalar_fneg_undef:
+; X32-SSE: # %bb.0:
+; X32-SSE-NEXT: fldz
+; X32-SSE-NEXT: retl
+;
+; X64-SSE-LABEL: scalar_fneg_undef:
+; X64-SSE: # %bb.0:
+; X64-SSE-NEXT: retq
%r = fneg float undef
ret float %r
}
define <4 x float> @fsub_neg0_undef(<4 x float> %Q) nounwind {
-; X32-SSE1-LABEL: fsub_neg0_undef:
-; X32-SSE1: # %bb.0:
-; X32-SSE1-NEXT: xorps {{\.LCPI.*}}, %xmm0
-; X32-SSE1-NEXT: retl
-;
-; X32-SSE2-LABEL: fsub_neg0_undef:
-; X32-SSE2: # %bb.0:
-; X32-SSE2-NEXT: retl
-;
-; X64-SSE1-LABEL: fsub_neg0_undef:
-; X64-SSE1: # %bb.0:
-; X64-SSE1-NEXT: xorps {{.*}}(%rip), %xmm0
-; X64-SSE1-NEXT: retq
-;
-; X64-SSE2-LABEL: fsub_neg0_undef:
-; X64-SSE2: # %bb.0:
-; X64-SSE2-NEXT: retq
+; X32-SSE-LABEL: fsub_neg0_undef:
+; X32-SSE: # %bb.0:
+; X32-SSE-NEXT: retl
+;
+; X64-SSE-LABEL: fsub_neg0_undef:
+; X64-SSE: # %bb.0:
+; X64-SSE-NEXT: retq
%r = fsub <4 x float> <float -0.0, float -0.0, float -0.0, float -0.0>, undef
ret <4 x float> %r
}
define <4 x float> @fneg_undef(<4 x float> %Q) nounwind {
-; X32-SSE1-LABEL: fneg_undef:
-; X32-SSE1: # %bb.0:
-; X32-SSE1-NEXT: xorps {{\.LCPI.*}}, %xmm0
-; X32-SSE1-NEXT: retl
-;
-; X32-SSE2-LABEL: fneg_undef:
-; X32-SSE2: # %bb.0:
-; X32-SSE2-NEXT: retl
-;
-; X64-SSE1-LABEL: fneg_undef:
-; X64-SSE1: # %bb.0:
-; X64-SSE1-NEXT: xorps {{.*}}(%rip), %xmm0
-; X64-SSE1-NEXT: retq
-;
-; X64-SSE2-LABEL: fneg_undef:
-; X64-SSE2: # %bb.0:
-; X64-SSE2-NEXT: retq
+; X32-SSE-LABEL: fneg_undef:
+; X32-SSE: # %bb.0:
+; X32-SSE-NEXT: retl
+;
+; X64-SSE-LABEL: fneg_undef:
+; X64-SSE: # %bb.0:
+; X64-SSE-NEXT: retq
%r = fneg <4 x float> undef
ret <4 x float> %r
}
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